Patents by Inventor Brian Goolsby

Brian Goolsby has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070272952
    Abstract: An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the electronic device may be formed by forming an oxidation mask over the first semiconductor portion. A second semiconductor layer can be formed over the second semiconductor portion of the first semiconductor layer and have a different composition compared to the first semiconductor layer. An oxidation can be performed, and a concentration of a semiconductor element (e.g., germanium) within the second portion of the first semiconductor layer can be increased. In another embodiment, a selective condensation may be performed, and a field isolation region can be formed between the first and second portions of the first semiconductor layer.
    Type: Application
    Filed: August 10, 2007
    Publication date: November 29, 2007
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Voon-Yew Thean, Brian Goolsby, Linda McCormick, Bich-Yen Nguyen, Colita Parker, Mariam Sadaka, Victor Vartanian, Ted White, Melissa Zavala
  • Patent number: 7238561
    Abstract: A method for making a semiconductor device is provided herein. In accordance with the method, a semiconductor structure is provided which comprises a substrate (201) with a gate structure (209) disposed thereon, wherein the gate structure comprises a gate electrode (227) and at least one spacer structure (215, 217), and wherein the substrate comprises a first semiconductor material. A first trench (231) is created in the substrate adjacent to the gate structure through the use of a first etch. The gate electrode is then etched with a second etch. Preferably, the minimum cumulative reduction in thickness of the gate electrode from the first and second etches is dg, the maximum depth of the first and second trenches after the first and second etches is dt, and dg?dt.
    Type: Grant
    Filed: August 2, 2005
    Date of Patent: July 3, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Da Zhang, Veer Dhandapani, Brian Goolsby, Bich-Yen Nguyen
  • Publication number: 20070108481
    Abstract: An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the electronic device may be formed by forming an oxidation mask over the first semiconductor portion. A second semiconductor layer can be formed over the second semiconductor portion of the first semiconductor layer and have a different composition compared to the first semiconductor layer. An oxidation can be performed, and a concentration of a semiconductor element (e.g., germanium) within the second portion of the first semiconductor layer can be increased. In another embodiment, a selective condensation may be performed, and a field isolation region can be formed between the first and second portions of the first semiconductor layer.
    Type: Application
    Filed: November 14, 2005
    Publication date: May 17, 2007
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Voon-Yew Thean, Brian Goolsby, Linda McCormick, Bich-Yen Nguyen, Colita Parker, Mariam Sadaka, Victor Vartanian, Ted White, Melissa Zavala
  • Publication number: 20070032003
    Abstract: A method for making a semiconductor device is provided herein. In accordance with the method, a semiconductor structure is provided which comprises a substrate (201) with a gate structure (209) disposed thereon, wherein the gate structure comprises a gate electrode (227) and at least one spacer structure (215, 217), and wherein the substrate comprises a first semiconductor material. A first trench (231) is created in the substrate adjacent to the gate structure through the use of a first etch. The gate electrode is then etched with a second etch. Preferably, the minimum cumulative reduction in thickness of the gate electrode from the first and second etches is dg, the maximum depth of the first and second trenches after the first and second etches is dt, and dg?dt.
    Type: Application
    Filed: August 2, 2005
    Publication date: February 8, 2007
    Inventors: Da Zhang, Veer Dhandapani, Brian Goolsby, Bich-Yen Nguyen
  • Publication number: 20060292773
    Abstract: A patterned polysilicon gate is over a metal layer that is over a gate dielectric layer, which in turn is over a semiconductor substrate. A thin layer of material is conformally deposited over the polysilicon gate and the exposed metal layer and then etched back to form a sidewall spacer on the polysilicon gate and to re-expose the previously exposed portion of the metal layer. The re-exposed metal layer is etched using an etchant that is selective to the gate dielectric material and the sidewall spacer. Even though this etch is substantially anisotropic, it has an isotropic component that would etch the sidewall of the polysilicon gate but for the protection provided by the sidewall spacer. After the re-exposed metal has been removed, a transistor is formed in which the metal layer sets the work function of the gate of the transistor.
    Type: Application
    Filed: June 24, 2005
    Publication date: December 28, 2006
    Inventors: Brian Goolsby, Bruce White
  • Publication number: 20060286736
    Abstract: An electronic device is formed by forming a first and second layer overlying a plurality of transistor locations. An etch is performed to remove portions of the first and second layers to expose a portion of the plurality of transistor locations, while other portions of the first and second layer remain to protect other transistor locations. Subsequently, source/drain locations of the exposed transistor locations are etched along with the remaining portion of the second layer. The etch is substantially terminated by removing the portion of the second layer using an end-point detection technique involving the first layer. Subsequently an epitaxial layer is formed in the source/drain recesses to provide stress on a channel region of the transistor locations.
    Type: Application
    Filed: June 15, 2005
    Publication date: December 21, 2006
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Marius Orlowski, Brian Goolsby
  • Publication number: 20060148196
    Abstract: A method of forming a transistor with recessed source/drains in an silicon-on-insulator (SOI) wafer includes forming isolation structures in an active layer of the wafer, where the isolation structures preferably extend through the active layer to a BOX layer of the wafer. An upper portion of the active layer is removed to form a transistor channel structure. A gate dielectric is formed on the channel structure and a gate structure is formed on the gate dielectric. Etching through exposed portions of the gate dielectric, channel structure, and BOX layer is performed and source/drain structures are then grown epitaxially from exposed portions of the substrate bulk. The isolation structure and the BOX layer are both comprised primarily of silicon oxide and the thickness of the isolation structure prevents portions of the BOX layer from being etched.
    Type: Application
    Filed: January 3, 2005
    Publication date: July 6, 2006
    Inventors: Voon-Yew Thean, Brian Goolsby, Bich-Yen Nguyen, Thien Nguyen, Tab Stephens
  • Publication number: 20060063364
    Abstract: A metal layer is formed over a metal oxide, where the metal oxide is formed over a semiconductor substrate. A predetermined critical dimension of the metal layer is determined. A first etch is performed to etch the metal layer down to the metal oxide and form footings at the sidewalls of the metal layer. A second etch to remove the footings to target a predetermined critical dimension, wherein the second etch is selective to the metal oxide. In one embodiment, a conductive layer is formed over the metal layer. The bulk of the conductive layer may be etched leaving a portion in contact with the metal layer. Next, the portion left in contact with the metal layer may be etched using chemistry selective to the metal layer.
    Type: Application
    Filed: September 17, 2004
    Publication date: March 23, 2006
    Inventors: Tab Stephens, Brian Goolsby, Bich-Yen Nguyen, Voon-Yew Thean
  • Publication number: 20060030093
    Abstract: A method for forming at least a portion of a semiconductor device includes providing a substrate and epitaxially forming an etch stop layer over the substrate. A first layer is provided over the etch stop layer, wherein the first layer is selectively etchable with regard to the etch stop layer. A structure is provided over a region of the first layer, wherein the region is not all of the first layer. In addition, the method includes etching at least a portion of the first layer that is outside of the region, wherein the etch stop layer is used an as etch stop. A strained layer is epitaxially grown in the etch-recessed region.
    Type: Application
    Filed: August 6, 2004
    Publication date: February 9, 2006
    Inventors: Da Zhang, Brian Goolsby, Eric Luckowski, Bich-Yen Nguyen, Mariam Sadaka, Voon-Yew Thean, Ted White