Patents by Inventor Brian Grayson

Brian Grayson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9569361
    Abstract: According to one general aspect, an apparatus may include a cache pre-fetcher, and a pre-fetch scheduler. The cache pre-fetcher may be configured to predict, based at least in part upon a virtual address, data to be retrieved from a memory system. The pre-fetch scheduler may be configured to convert the virtual address of the data to a physical address of the data, and request the data from one of a plurality of levels of the memory system. The memory system may include a plurality of levels, each level of the memory system configured to store data.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: February 14, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Arun Radhakrishnan, Kevin Lepak, Rama Gopal, Murali Chinnakonda, Karthik Sundaram, Brian Grayson
  • Patent number: 9286073
    Abstract: Dynamically predicting a Read-After-Write (RAW) hazard by employing a variable confidence score attributed to a RAW Resynchronization Predictor (RRP) for sampling the RRP at timing periods dynamically adjusted based on the confidence score to optimize prediction of the RAW hazard.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: March 15, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Gerald Zuraski, Paul Kitchin, Brian Grayson
  • Publication number: 20160054997
    Abstract: A computing system includes: an instruction dispatch module configured to receive an address stream; a prefetch module, coupled to the instruction dispatch module, configured to: train to concurrently detect a single-stride pattern or a multi-stride pattern from the address stream, speculatively fetch a program data based on the single-stride pattern or the multi-stride pattern, and continue to train for the single-stride pattern with a larger value for a stride count or for the multi-stride pattern.
    Type: Application
    Filed: August 21, 2015
    Publication date: February 25, 2016
    Inventors: Arun Radhakrishnan, Karthik Sundaram, Brian Grayson
  • Publication number: 20150199276
    Abstract: According to one general aspect, a method may include receiving, by a pre-fetch unit, a demand to access data stored at a memory address. The method may include determining if a first portion of the memory address matches a prior defined region of memory. The method may further include determining if a second portion of the memory address matches a previously detected pre-fetched address portion. The method may also include, if the first portion of the memory address matches the prior defined region of memory, and the second portion of the memory address matches the previously detected pre-fetched address portion, confirming that a pre-fetch pattern is associated with the memory address.
    Type: Application
    Filed: August 4, 2014
    Publication date: July 16, 2015
    Inventors: Arun RADHAKRISHNAN, Karthik SUNDARAM, Brian GRAYSON
  • Publication number: 20150199275
    Abstract: According to one general aspect, an apparatus may include a cache pre-fetcher, and a pre-fetch scheduler. The cache pre-fetcher may be configured to predict, based at least in part upon a virtual address, data to be retrieved from a memory system. The pre-fetch scheduler may be configured to convert the virtual address of the data to a physical address of the data, and request the data from one of a plurality of levels of the memory system. The memory system may include a plurality of levels, each level of the memory system configured to store data.
    Type: Application
    Filed: July 7, 2014
    Publication date: July 16, 2015
    Inventors: Arun RADHAKRISHNAN, Kevin LEPAK, Rama GOPAL, Murali CHINNAKONDA, Karthik SUNDARAM, Brian GRAYSON
  • Publication number: 20150193334
    Abstract: Dynamically predicting a Read-After-Write (RAW) hazard by employing a variable confidence score attributed to a RAW Resynchronization Predictor (RRP) for sampling the RRP at timing periods dynamically adjusted based on the confidence score to optimize prediction of the RAW hazard.
    Type: Application
    Filed: November 25, 2014
    Publication date: July 9, 2015
    Inventors: Gerald ZURASKI, Paul KITCHIN, Brian GRAYSON
  • Patent number: 7178600
    Abstract: Methods and apparatus for utilizing a downhole deployment valve (DDV) to isolate a pressure in a portion of a bore are disclosed. Any combination of fail safe features may be used with or incorporated into the DDV such as redundant valve members, an upward opening flapper valve or a metering flapper below a sealing valve. In one aspect, a barrier or diverter located in the bore above a valve member of the DDV permits passage through the bore when the valve member is open and actuates when the valve member is closed. Once actuated, the barrier or diverter either stops or diverts any dropped objects prior to the dropped object reaching and potentially damaging the valve member. In another aspect, the tool string tripped in above the DDV includes an acceleration actuated brake that anchors the tool string to a surrounding tubular if the tool string is dropped.
    Type: Grant
    Filed: February 20, 2004
    Date of Patent: February 20, 2007
    Assignee: Weatherford/Lamb, Inc.
    Inventors: Mike A. Luke, Tom Fuller, Darrell Johnson, David Brunnert, Brian Grayson, David Pavel, R. K. Bansal
  • Publication number: 20060248279
    Abstract: Prefetching across a page boundary in a data processing system. The system determines whether a prefetch will cross a page boundary of memory, and if so, it determines whether a translation source has an entry corresponding to the virtual address of the prefetch. If the translation source has an entry corresponding the virtual address, a physical address of the virtual address is used to prefetch the information.
    Type: Application
    Filed: May 2, 2005
    Publication date: November 2, 2006
    Inventors: Hassan Al-Sukhni, Brian Grayson, James Holt, Matt Smittle, Michael Snyder
  • Publication number: 20060248281
    Abstract: Generating a hashed value of the program counter in a data processing system. The hashed value can be used for prefetching in the data processing system. In some examples, the hashed value is used to identify whether a load instruction associated with the hashed value has an address that is part of a strided stream in an address stream. In some examples, the hashed value is a subset of bits of the bits of the program counter. In other examples, the hashed value may be derived in other ways from the program counter.
    Type: Application
    Filed: May 2, 2005
    Publication date: November 2, 2006
    Inventors: Hassan Al-Sukhni, James Holt, Matt Smittle, Michael Snyder, Brian Grayson
  • Publication number: 20060136696
    Abstract: A memory management unit (MMU) has a cache for storing address translation entries (ATEs) corresponding to virtual addresses. If an ATE is present for a requested virtual address, then it is translated to the physical address and sent to main memory. If the MMU cache misses, the virtual address is hashed to obtain the physical address for a group of ATEs. After hashing, a decision is made whether to prefetch the group of ATEs or not. If so, the group is loaded into the data cache. Another determination is made; in this case whether to continue or not. If the request is not valid, the process is terminated. If the request is still valid, then a tablewalk is performed on the group to find the matching entry, which is loaded into the MMU cache. The virtual address is translated to obtain the physical address which is sent to main memory.
    Type: Application
    Filed: December 16, 2004
    Publication date: June 22, 2006
    Inventor: Brian Grayson
  • Publication number: 20040251032
    Abstract: Methods and apparatus for utilizing a downhole deployment valve (DDV) to isolate a pressure in a portion of a bore are disclosed. Any combination of fail safe features may be used with or incorporated into the DDV such as redundant valve members, an upward opening flapper valve or a metering flapper below a sealing valve. In one aspect, a barrier or diverter located in the bore above a valve member of the DDV permits passage through the bore when the valve member is open and actuates when the valve member is closed. Once actuated, the barrier or diverter either stops or diverts any dropped objects prior to the dropped object reaching and potentially damaging the valve member. In another aspect, the tool string tripped in above the DDV includes an acceleration actuated brake that anchors the tool string to a surrounding tubular if the tool string is dropped.
    Type: Application
    Filed: February 20, 2004
    Publication date: December 16, 2004
    Applicant: Weatherford/Lamb, Inc.
    Inventors: Mike A. Luke, Tom Fuller, Darrell Johnson, David Brunnert, Brian Grayson, David Pavel, R. K. Bansal