Patents by Inventor Brian Hang Wai Yang
Brian Hang Wai Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8711849Abstract: A network switch includes an input layer to receive a data stream with a set of cells. Each cell includes data and a header to designate a destination device. The input layer includes a set of input layer circuits. A selected input layer circuit of the set of input layer circuits receives the data stream. The selected input layer circuit includes a set of queues corresponding to a set of destination devices. The selected input layer circuit is configured to assign a selected cell from the data stream to a selected queue of the set of queues. The selected queue corresponds to a selected destination device specified by the header of the selected cell. An intermediate layer includes a set of intermediate layer circuits, each intermediate layer circuit has a set of buffers corresponding to the set of destination devices.Type: GrantFiled: November 15, 2010Date of Patent: April 29, 2014Assignee: NetLogic Microsystems, Inc.Inventors: Kai-Yeung (Sunny) Siu, Brian Hang Wai Yang, Mizanur M. Rahman
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Patent number: 8594087Abstract: A packet duplication control system including an input port for receiving a packet and a plurality of output ports for outputting duplications of the packet is disclosed. The duplications can be suitable to support a Virtual Local Area Network (VLAN) system. The duplications can be controlled by descriptors arranged in a linked-list table. Also, the descriptors can have encoding formats, such as contiguous range encoding, non-contiguous range encoding, and discrete encoding. Further, the linked-list table can include at least one shared descriptor.Type: GrantFiled: October 17, 2003Date of Patent: November 26, 2013Assignee: Netlogic Microsystems, Inc.Inventors: Gaurav Singh, Govind Malalur, Brian Hang Wai Yang
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Patent number: 8577921Abstract: A search key lookup system including a hash table having a plurality of entries and a function generator is disclosed. The function generator can be coupled to the hash table and configured to receive a key and to provide a first function and a second function. The first function can be a Cyclic Redundancy Code (CRC) type function and the second function can be an Error Checking and Correcting (ECC) type function. Further, an address of the table can include a concatenation of the results of the CRC and the ECC type functions.Type: GrantFiled: September 25, 2009Date of Patent: November 5, 2013Assignee: Netlogic Microsystems, Inc.Inventor: Brian Hang Wai Yang
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Patent number: 8514873Abstract: An apparatus and method to receive first service request signals and second service request signals from virtual signal queues, to map the virtual signal queues according to a first mapping, to arbitrate the first service request signals in accordance with the first mapping of the virtual signal queues, and to re-map the virtual signal queues according to a second mapping, different from the first mapping, to allow arbitrating of the second service request signals in accordance with the second mapping of the virtual signal queues.Type: GrantFiled: September 24, 2010Date of Patent: August 20, 2013Assignee: NetLogic Microsystems, Inc.Inventors: Brian Hang Wai Yang, Kai-Yeung (Sunny) Siu, Mizanur M. Rahman, Wei-Han Lien, Gaurav Singh
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Patent number: 8472312Abstract: A stacked switch using a resilient packet ring protocol comprises a plurality of switch modules coupled to one another in a ring topology and each having a plurality of external terminals for interfacing with external devices. Each switch module includes an external interface for communicating with the external terminals, the external interface configured to communicate using a communication protocol; and an internal interface for communicating with other switches, the internal interface using a resilient packet ring (RPR) protocol. Advantages of the invention include the ability to flexibly create a high performance stacked switch with advanced features.Type: GrantFiled: September 25, 2009Date of Patent: June 25, 2013Assignee: NetLogic Microsystems, Inc.Inventors: Brian Hang Wai Yang, Ken K. Ho, Aamer Latif
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Patent number: 7934198Abstract: A prefix matching apparatus for directing information to a destination port includes a memory configured to store a piece of data including an address and a plurality of levels each including a plurality of memory locations, the levels each representing a unique address space. A controller is coupled to the memory and to the plurality of levels, and is configured to read the data address and to direct the data to the next level associated with a unique address space associated with the data address. In one embodiment, the controller is configured to match the data address prefix to a plurality of addresses associated with the unique address spaces. Advantages of the invention include fast switch decisions and low switch latency.Type: GrantFiled: October 18, 2004Date of Patent: April 26, 2011Assignee: NetLogic Microsystems, Inc.Inventors: Frederick R. Gruner, Gaurav Singh, Elango Ganesan, Samir C. Vora, Christopher M. Eccles, Brian Hang Wai Yang
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Publication number: 20110085553Abstract: A network switch includes an input layer to receive a data stream with a set of cells. Each cell includes data and a header to designate a destination device. The input layer includes a set of input layer circuits. A selected input layer circuit of the set of input layer circuits receives the data stream. The selected input layer circuit includes a set of queues corresponding to a set of destination devices. The selected input layer circuit is configured to assign a selected cell from the data stream to a selected queue of the set of queues. The selected queue corresponds to a selected destination device specified by the header of the selected cell. An intermediate layer includes a set of intermediate layer circuits, each intermediate layer circuit has a set of buffers corresponding to the set of destination devices.Type: ApplicationFiled: November 15, 2010Publication date: April 14, 2011Applicant: NETLOGIC MICROSYSTEMS, INC.Inventors: Kai-Yeung (Sunny) SIU, Brian Hang Wai YANG, Mizanur M. RAHMAN
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Publication number: 20110013643Abstract: The invention relates to a crossbar switch controller including an input terminal configured to receive a set of service request signals from a set of virtual output queues each comprising a set of packets. The invention also includes a matrix circuit coupled to the input terminal and configured to represent the set of service request signals in the form of a matrix, wherein each service request signal is described by a row position M and a column position N. The invention further includes an output terminal configured to receive a portion of the set of packets during an epoch, an arbiter circuit configured to iteratively scan the matrix during the epoch and issue the set of grant signals to the virtual output queues to determine which service requests are granted, and an arbiter controller configured to initiate the arbiter circuit with an array of non-conflicting matrix elements.Type: ApplicationFiled: September 24, 2010Publication date: January 20, 2011Applicant: NETLOGIC MICROSYSTEMS, INC.Inventors: Brian Hang Wai Yang, Kai-Yeung (Sunny) Siu, Mizanur M. Rahman, Wei-Han Lien, Gaurav Singh
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Publication number: 20100017681Abstract: A search key lookup system including a hash table having a plurality of entries and a function generator is disclosed. The function generator can be coupled to the hash table and configured to receive a key and to provide a first function and a second function. The first function can be a Cyclic Redundancy Code (CRC) type function and the second function can be an Error Checking and Correcting (ECC) type function. Further, an address of the table can include a concatenation of the results of the CRC and the ECC type functions.Type: ApplicationFiled: September 25, 2009Publication date: January 21, 2010Inventor: Brian Hang Wai Yang
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Patent number: 7617241Abstract: A search key lookup system including a hash table having a plurality of entries and a function generator is disclosed. The function generator can be coupled to the hash table and configured to receive a key and to provide a first function and a second function. The first function can be a Cyclic Redundancy Code (CRC) type function and the second function can be an Error Checking and Correcting (ECC) type function. Further, an address of the table can include a concatenation of the results of the CRC and the ECC type functions.Type: GrantFiled: November 7, 2003Date of Patent: November 10, 2009Assignee: RMI CorporationInventor: Brian Hang Wai Yang
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Patent number: 7613201Abstract: A stacked switch using a resilient packet ring protocol comprises a plurality of switch modules coupled to one another in a ring topology and each having a plurality of external terminals for interfacing with external devices. Each switch module includes an external interface for communicating with the external terminals, the external interface configured to communicate using a communication protocol; and an internal interface for communicating with other switches, the internal interface using a resilient packet ring (RPR) protocol. Advantages of the invention include the ability to flexibly create a high performance stacked switch with advanced features.Type: GrantFiled: April 16, 2004Date of Patent: November 3, 2009Assignee: RMI CorporationInventors: Brian Hang Wai Yang, Ken K. Ho, Aamer Latif
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Patent number: 7586911Abstract: A packet transmit queue control system including a first data structure, a second data structure, a packet controller, and a port transmit controller is disclosed. The first data structure can include a plurality of linked-list data structures and can store unicast type packet pointers. The second data structure can include a plurality of first-in first-out (FIFO) structures and can store multicast type packet pointers. The packet controller can receive a first sequence of unicast and/or multicast type packets. The port transmit controller can provide a second sequence of the unicast and/or multicast type packets. Further, each of the plurality of FIFO structures can correspond to an output port of the system.Type: GrantFiled: October 17, 2003Date of Patent: September 8, 2009Assignee: RMI CorporationInventors: Wei-han Lien, Brian Hang Wai Yang, Sridhar Subramanian
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Patent number: 7536631Abstract: A communication circuit for verified communication comprising a transmitter having input terminals to receive a data word, an encoder configured to encode the data word to create an encoded word different from the data word, and output terminals configured to transmit the data word and the encoded word. A receiver is coupled to the transmitter and includes input terminals to receive the data word as a received word and the encoded word, a decoder configured to decode the encoded word to create a decoded word, and a comparator configured to compare the received word and the decoded word to create a select signal, and a selector responsive to the select signal and configured to select the received data word or the decoded word based at least in part on the select signal. Advantages of the invention include the ability to verify redundant received data without decreasing bandwidth or increasing latency.Type: GrantFiled: June 3, 2003Date of Patent: May 19, 2009Assignee: RMI CorporationInventors: Brian Hang Wai Yang, Kai-Yeung Siu, Mizanur M. Rahman, Ken Yeung, Hsi-Tung Huang
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Publication number: 20090034517Abstract: The invention relates to a crossbar switch controller including an input terminal configured to receive a set of service request signals from a set of virtual output queues each comprising a set of packets. The invention also includes a matrix circuit coupled to the input terminal and configured to represent the set of service request signals in the form of a matrix, wherein each service request signal is described by a row position M and a column position N. The invention further includes an output terminal configured to receive a portion of the set of packets during an epoch, an arbiter circuit configured to iteratively scan the matrix during the epoch and issue the set of grant signals to the virtual output queues to determine which service requests are granted, and an arbiter controller configured to initiate the arbiter circuit with an array of non-conflicting matrix elements.Type: ApplicationFiled: July 9, 2008Publication date: February 5, 2009Inventors: Brian Hang Wai Yang, Kai-Yeung (Sunny) Siu, Mizanur M. Rahman, Wei-Han Lien, Gaurav Singh
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Patent number: 7471682Abstract: A configurable lookup table system including a first controller coupled to a first lookup table and a second controller coupled to a second lookup table is disclosed. The first controller configures the first lookup table for a first type lookup, which can be a Layer 2 or Media Access Control (MAC) type. The second controller configures the second lookup table based on a mode determination. If in a first mode, the second lookup table can be configured for a second type lookup, which can be a Layer 3 or Internet Protocol (IP) type. If in a second mode, the second lookup table can be configured for the first type lookup. This approach provides an efficient scheme for controlling and using multiple internal lookup tables for a variety of product configurations.Type: GrantFiled: October 17, 2003Date of Patent: December 30, 2008Assignee: RMI CorporationInventors: Gaurav Singh, Ali Kani, Kiran Kattel, Sridhar Subramanian, Brian Hang Wai Yang
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Publication number: 20080281789Abstract: A search engine system including a memory bank coupled to a bank selection signal, mask logic for receiving constructed keys and incoming key masks and for providing masked keys, hash function blocks for receiving at least two of the masked keys and for providing at least three hash function outputs, and multiplexers for receiving hash function outputs and for providing the bank selection signal is disclosed. Also, the system can allow for local masking of the constructed keys using local mask fields. The hash function can be a Cyclic Redundancy Code (CRC) type function. The memory bank can be arranged as buckets of entries and can be implemented as a standard static random access memory (SRAM). Further, the system can be configured to operate in either a shared mode for sharing hash function outputs or a non-shared mode whereby hash function outputs can be designated for particular portions of the memory bank.Type: ApplicationFiled: May 10, 2007Publication date: November 13, 2008Applicant: Raza Microelectronics, Inc.Inventors: Sophia W. Kao, Govind Malalur, Brian Hang Wai Yang
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Patent number: 7234019Abstract: A search engine system including a memory bank coupled to a bank selection signal, mask logic for receiving constructed keys and incoming key masks and for providing masked keys, hash function blocks for receiving at least two of the masked keys and for providing at least three hash function outputs and multiplexers for receiving hash function outputs, and for providing the bank selection signal is disclosed. Also, the system can allow for local masking of the constructed keys using local mask fields. The hash function can be a Cyclic Redundancy Code (CRC) type function. The memory bank can be arranged as buckets of entries and can be implemented as a standard static random access memory (SRAM). Further, the system can be configured to operate in either a shared mode for sharing hash function outputs or a non-shared mode whereby hash function outputs can be designated for particular portions of the memory bank.Type: GrantFiled: December 12, 2003Date of Patent: June 19, 2007Assignee: Raza Microelectronics, Inc.Inventors: Sophia W. Kao, Govind Malalur, Brian Hang Wai Yang
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Patent number: 7174441Abstract: A configurable lookup table extension system including a plurality of lookup tables arranged in an internal memory, an external memory, and a flexible controller configured to couple at least one of the plurality of lookup tables to the external memory through a single memory interface is disclosed. Implementations of this system can support the flexible allocation of IP and MAC table entries so that a router/switch can flexibly support applications suited to a particular allocation. This approach provides an efficient scheme for extending multiple internal tables to external memory via a single external interface. Further, such extensibility is also programable to allow the size and number of external tables to be configured by software. This solution can provide the flexibility of customizing table sizes for different markets and/or customer requirements.Type: GrantFiled: October 17, 2003Date of Patent: February 6, 2007Assignee: Raza Microelectronics, Inc.Inventors: Gaurav Singh, Frederick R. Gruner, Brian Hang Wai Yang