Patents by Inventor Brian Hardy COBB
Brian Hardy COBB has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11836562Abstract: The present invention provides for a RFID tag assembly that is suitable for operation with at least one RFID reader assembly. The RFID tag assembly comprises, inter alia, an antenna member for transmitting and/or receiving an RFID signal, and at least one integrated circuit (IC) for processing the RFID signal and which is configured to communicate, alternatingly and sequentially in time, a first signal transmission and at least one second signal transmission, each defined by a plurality of predetermined signal transmission parameters, to the at least one RFI D reader assembly, utilising time-division multiplexing, wherein the at least one first signal transmission differs from the at least one second signal transmission in at least one of said plurality of predetermined signal transmission parameters.Type: GrantFiled: December 3, 2019Date of Patent: December 5, 2023Assignee: PRAGMATIC PRINTING LTD.Inventors: Brian Hardy Cobb, Scott White
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Publication number: 20230387145Abstract: A structure is disclosed, comprising: a first field effect transistor, FET, comprising a first source terminal, a first drain terminal, a first layer or body of semiconductive material arranged to provide a first semiconductive channel connecting the first source terminal to the first drain terminal, and a gate terminal arranged with respect to the first semiconductive channel such that a conductivity of the first semiconductive channel may be controlled by application of a voltage to the gate terminal; and a second FET comprising a second source terminal, a second drain terminal, a second layer or body of semiconductive material arranged to provide a second semiconductive channel connecting the second source terminal to the second drain terminal, and the gate terminal, the second conductive channel being arranged with respect to the gate terminal such that a conductivity of the second channel may be controlled by application of a voltage to the gate terminal.Type: ApplicationFiled: August 8, 2023Publication date: November 30, 2023Inventors: Richard PRICE, Catherine RAMSDALE, Brian Hardy COBB, Feras ALKHALIL
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Publication number: 20220343128Abstract: The present invention provides for a RFID tag assembly that is suitable for operation with at least one RFID reader assembly. The RFID tag assembly comprises, inter alia, an antenna member for transmitting and/or receiving an RFID signal, and at least one integrated circuit (1C) for processing the RFID signal and which is configured to communicate, alternatingly and sequentially in time, a first signal transmission and at least one second signal transmission, each defined by a plurality of predetermined signal transmission parameters, to the at least one RFI D reader assembly, utilising time-division multiplexing, wherein the at least one first signal transmission differs from the at least one second signal transmission in at least one of said plurality of predetermined signal transmission paameters.Type: ApplicationFiled: December 3, 2019Publication date: October 27, 2022Inventors: Brian Hardy COBB, Scott WHITE
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Publication number: 20220027701Abstract: The present invention provides for a RFID tag assembly that is suitable for operation with at least one RFID reader assembly. The RFID tag assembly comprises, inter alia, an antenna member for transmitting and/or receiving an RFID signal, and at least one integrated circuit (1C) for processing the RFID signal and which is configured to communicate, alternatingly and sequentially in time, a first signal transmission and at least one second signal transmission, each defined by a plurality of predetermined signal transmission parameters, to the at least one RFI D reader assembly, utilising time-division multiplexing, wherein the at least one first signal transmission differs from the at least one second signal transmission in at least one of said plurality of predetermined signal transmission paameters.Type: ApplicationFiled: December 3, 2019Publication date: January 27, 2022Inventors: Brian Hardy COBB, Scott WHITE
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Publication number: 20210265395Abstract: A structure is disclosed, comprising: a first field effect transistor, FET, comprising a first source terminal, a first drain terminal, a first layer or body of semiconductive material arranged to provide a first semiconductive channel connecting the first source terminal to the first drain terminal, and a gate terminal arranged with respect to the first semiconductive channel such that a conductivity of the first semiconductive channel may be controlled by application of a voltage to the gate terminal; and a second FET comprising a second source terminal, a second drain terminal, a second layer or body of semiconductive material arranged to provide a second semiconductive channel connecting the second source terminal to the second drain terminal, and the gate terminal, the second conductive channel being arranged with respect to the gate terminal such that a conductivity of the second channel may be controlled by application of a voltage to the gate terminal.Type: ApplicationFiled: May 10, 2021Publication date: August 26, 2021Inventors: Richard PRICE, Catherine RAMSDALE, Brian Hardy COBB, Feras ALKHALIL
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Patent number: 11004875Abstract: A structure is disclosed, comprising: a first field effect transistor, FET, comprising a first source terminal, a first drain terminal, a first layer or body of semiconductive material arranged to provide a first semiconductive channel connecting the first source terminal to the first drain terminal, and a gate terminal arranged with respect to the first semiconductive channel such that a conductivity of the first semiconductive channel may be controlled by application of a voltage to the gate terminal; and a second FET comprising a second source terminal, a second drain terminal, a second layer or body of semiconductive material arranged to provide a second semiconductive channel connecting the second source terminal to the second drain terminal, and the gate terminal, the second conductive channel being arranged with respect to the gate terminal such that a conductivity of the second channel may be controlled by application of a voltage to the gate terminal.Type: GrantFiled: March 27, 2018Date of Patent: May 11, 2021Assignee: PRAGMATIC PRINTING LTD.Inventors: Richard Price, Catherine Ramsdale, Brian Hardy Cobb, Feras Alkhalil
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Publication number: 20210003460Abstract: Measurement apparatus, for generating a first output signal indicative of a measurand, comprises: a first oscillator circuit and a second oscillator circuit, each oscillator circuit being arranged to generate a respective oscillating output signal and comprising at least a respective first component having a property determining a respective output frequency of the respective oscillating output signal; a sensor for sensing said measurand, the sensor comprising said first component of the first oscillator circuit, said property of said first component of the first oscillator circuit being dependent upon said measurand; and circuitry arranged to receive said oscillating output signals and generate said first output signal, said first output signal being indicative of a number of cycles of one of the first and second oscillating output signals in a time period determined by a period of the other of said first and second oscillating output signals.Type: ApplicationFiled: March 5, 2019Publication date: January 7, 2021Inventors: Brian Hardy COBB, Joao DE OLIVEIRA, Thomas CLARK, Kenneth David WILLIAMSON
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Patent number: 10636351Abstract: A conformable matrix display device is provided with row conductors on the conformable carrier, each for a respective row of the matrix of pixel circuits. Each row conductor has serpentine trajectories in spaces between the pixel circuits in the respective row. Power supply voltage and selection pulse signals are transmitted over the same row conductors. Each row conductor is connected to supply voltage and selection inputs of the pixel circuits in the respective row. Each pixel circuit has a pulse transmission circuit coupled between the selection input and the control input of a de-multiplexing circuit for de-multiplexing data signals on column conductors. In this way the power supply voltage and the selection signal can be supplied making shared use of space between the pixel circuits. Thus the number of conductors in the matrix display device is reduced, which enables a greater distance between the conductors and/or bends in the conductors, which makes the circuit more stretchable and/or bendable.Type: GrantFiled: May 26, 2017Date of Patent: April 28, 2020Assignees: Nederlandse Organisatie voor toegepast-natuurwetenschappelijk onderzoek TNO, IMEC vzwInventors: Brian Hardy Cobb, Jan Genoe
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Publication number: 20200035720Abstract: A structure is disclosed, comprising: a first field effect transistor, FET, comprising a first source terminal, a first drain terminal, a first layer or body of semiconductive material arranged to provide a first semiconductive channel connecting the first source terminal to the first drain terminal, and a gate terminal arranged with respect to the first semiconductive channel such that a conductivity of the first semiconductive channel may be controlled by application of a voltage to the gate terminal; and a second FET comprising a second source terminal, a second drain terminal, a second layer or body of semiconductive material arranged to provide a second semiconductive channel connecting the second source terminal to the second drain terminal, and the gate terminal, the second conductive channel being arranged with respect to the gate terminal such that a conductivity of the second channel may be controlled by application of a voltage to the gate terminal.Type: ApplicationFiled: March 27, 2018Publication date: January 30, 2020Inventors: Richard PRICE, Catherine RAMSDALE, Brian Hardy COBB, Feras ALKHALIL
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Publication number: 20190213947Abstract: A conformable matrix display device is provided with row conductors on the conformable carrier, each for a respective row of the matrix of pixel circuits. Each row conductor has serpentine trajectories in spaces between the pixel circuits in the respective row. Power supply voltage and selection pulse signals are transmitted over the same row conductors. Each row conductor is connected to supply voltage and selection inputs of the pixel circuits in the respective row. Each pixel circuit has a pulse transmission circuit coupled etween the selection input and the control input of a de-multiplexing circuit for de-multiplexing data signals on column conductors. In this way the power supply voltage and the selection signal can be supplied making shared use of space between the pixel circuits. Thus the number of conductors in the matrix display device is reduced, which enables a greater distance between the conductors and/or bends in the conductors, which makes the circuit more stretchable and/or bendable.Type: ApplicationFiled: May 26, 2017Publication date: July 11, 2019Applicants: Nederlandse Organisatie voor toegepast-natuurwetenschappelijk onderzoek TNO, IMEC vzwInventors: Brian Hardy COBB, Jan GENOE
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Patent number: 10326027Abstract: A TFT device is manufactured starting from a substrate with mutually insulated elongated strips of semi-conductor material. A stack of layers over the strips on the substrate, the stack comprising a gate electrode layer. A multi-level resist layer is provided over the gate electrode layer. The multi-level resist layer defines gate and source drain regions, the channel running in parallel with the direction of the strips. Gate portions in the resist layer cross source drain regions in the resist layer, overreaching the source drain regions on either side at least by a distance corresponding to a pitch of the strips.Type: GrantFiled: August 26, 2016Date of Patent: June 18, 2019Assignee: Nederlandse Organisatie voor toegepast-natuurwetenschappelijk onderzoek TNOInventor: Brian Hardy Cobb
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Publication number: 20190027613Abstract: A TFT device is manufactured starting from a substrate with mutually insulated elongated strips of semi-conductor material. A stack of layers over the strips on the substrate, the stack comprising a gate electrode layer. A multi-level resist layer is provided over the gate electrode layer. The multi-level resist layer defines gate and source drain regions, the channel running in parallel with the direction of the strips. Gate portions in the resist layer cross source drain regions in the resist layer, overreaching the source drain regions on either side at least by a distance corresponding to a pitch of the strips.Type: ApplicationFiled: August 26, 2016Publication date: January 24, 2019Applicant: Nederlandse Organisatie voor toegepast-natuurweten schappelijk onderzoek TNOInventor: Brian Hardy COBB