Abstract: An injection device for humidifying a reactor space and injecting and dispersing reagents into the humidified reactor space, including an exterior injection duct for high-velocity gas injection and at least one interior injector for reagent and humidifying agent injection as droplets with a droplet environment. The high-velocity gas ensuring the humidification of the liquid droplet environment and mixing and dispersion of the liquid reagent droplets into the reactor. A multiple injection device system and a method for operating the system are also described.

Abstract: The present invention relates to high-purity niobium monoxide powder (NbO) produced by a process of combining a mixture of higher niobium oxides and niobium metal powder or granules; heating and reacting the compacted mixture under controlled atmosphere to achieve temperature greater than about 1945° C., at which temperature the NbO is liquid; solidifying the liquid NbO to form a body of material; and fragmenting the body to form NbO particles suitable for application as capacitor anodes. The NbO product is unusually pure in composition and crystallography, and can be used for capacitors and for other electronic applications. The method of production of the NbO is robust, does not require high-purity feedstock, and can reclaim value from waste streams associated with the processing of NbO electronic components. The method of production also can be used to make high-purity NbO2 and mixtures of niobium metal/niobium monoxide and niobium monoxide/niobium dioxide.

Abstract: A memory device is described which has memory storage cells coupled to data bit lines. Sense amplifier circuits are provided to receive input from the data bit lines and produce an output in response thereto. The memory includes circuitry which shifts the input to the sense amplifiers. Data bit lines from a neighboring sense amplifier is shifted to another sense amplifier such that redundant memory storage cells and data bit lines can be substituted for defective ones.

Abstract: A multi-processor system has a number of processing elements interconnected by a network for transmitting data frames between the elements. Each element includes an application layer, a transport layer and a link layer. The application layer contains end-point processes each having an address space. The transport layer can allocate a buffer in the address space of a specified end-point process and return details of the buffer to the link layer. The link layer can write message data from a received data frame directly into the allocated buffer by direct memory access without buffering the message data in the link layer. In this way, copying is reduced, improving the efficiency of the system.

Abstract: A data processing element comprises at least one processor, a main memory, and a network coupler for coupling the processing element to a network. The network coupler includes a packing circuit for assembling the data frames into intermediate units of data, referred to as parcels, and a network coupler processor for assembling the parcels into datagrams in the main memory. Thus, the packing circuit relieves the network coupler processor of a substantial amount of low-level processing work.

Abstract: A multi-processor system has a plurality of processing elements interconnected by a network for transmitting data between the elements. Each of the elements has a status table, indicating that element's view of the statuses of all the elements in the system, and a reliability map, containing a bit for each element in the system, along with copies of the reliability maps of all the other elements in the system. Each element sets the bits in its reliability map to indicate which of the other elements it is in regular communication with. Whenever an element's own reliability map changes, the element sends a copy of that map to all the other elements. Whenever any bit changes in any of the reliability maps held by an element, that element uses the maps to perform a status re-evaluation of all the elements, and updates its status table. This provides a consensus voting mechanism which ensures that all elements arrive at the same view of the element statuses.

Abstract: A memory device is described which has memory storage cells coupled to data bit lines. Sense amplifier circuits are provided to receive input from the data bit lines and produce an output in response thereto. The memory includes circuitry which shifts the input to the sense amplifiers. Data bit lines from a neighboring sense amplifier is shifted to another sense amplifier such that redundant memory storage cells and data bit lines can be substituted for defective ones.

Abstract: A problem solving expert system is provided which is particularly useful in managing the health care of individual patients. A description of a problem (e.g., medical condition) and a proposed solution therefor (e.g., medical procedure) is entered via a user interface. A topical library is searched to identify information relevant to the problem and proposed solution. Access to the identified information is available in either a full text or synopsis format, to assist a user in assessing the appropriateness of the proposed solution. An inference engine provides a recommendation to the user as to the appropriateness of the proposed solution based on information entered via the user interface and rules associated with the inference engine. A user can interact with the inference engine in either a structured or guided mode.

Abstract: A semiconductor wafer has multiple individual dies containing integrated circuits arrayed for singulation and test cycling circuitry for test cycling individual dies. A passivation layer overlies the dies, with contact openings being provided through the passivation layer to Vcc and Vss pads. The semiconductor wafer also has Vcc and Vss buses provided atop the passivation layer and overlying the individual dies to connect with the underlying Vcc and Vss pads, respectively. In this manner, application of voltage to the Vcc and Vss buses provides simultaneous test cycling of all the underlying dies on the semiconductor wafer. A semiconductor wafer processing fixture for conducting the burn-in test cycling of such a semiconductor wafer is also disclosed. The fixture has a wafer cavity sized to receive and register the semiconductor wafer in a selected orientation and an electrical connector having pins designed to contact the overlying busing structure on the semiconductor wafer.

Abstract: A semiconductor wafer comprises a plurality of individual dies containing integrated circuits which are substantially isolated from each other. The wafer is severable between the dies to physically singulate the dies from each other. The wafer includes test cycling circuitry for test cycling the individual dies. A Vcc bus and a Vss bus overly a passivation layer and are electrically connected through the passivation layer with Vcc and Vss pads associated with the individual dies.

Abstract: A method of processing and testing a semiconductor wafer containing an array of integrated circuit dies comprises: a) providing die test cycling circuitry on the wafer b) etching contact openings through a passivation layer atop the wafer to Vcc and Vss pads associated with individual dies; c) patterning a layer of conductive material atop the water to provide a Vcc bus and a Vss bus which interconnect with the Vcc and Vss pads respectively, the Vcc bus electrically connecting with the test cycling circuitry; d) burn-in testing the wafer with selected voltages being applied to the Vss and Vcc buses e) etching the Vcc bus and Vss bus from the wafer; f) etching contact openings through the passivation layer to conductive pads on individual dies; g) testing the individual dies for operability by engaging the conductive pads with testing equipment; h) identifying operable dies; i) singulating the dies; and j) collecting the operable dies.