Abstract: This invention relates generally to a garage door control system. A system includes, but is not limited to: sensor devices that detect a position of a garage door from a floor using a distance from the devices and the door, the devices being mounted at a far end of a horizontal guidance track; a control unit coupled to the sensor devices, the control unit including at least a computer processor; a power distribution and control relay unit; a wireless communication interface operable to communicate wirelessly; and a link connected to the garage door motor; and a user interface unit in place of the existing garage door button, wherein the user interface receives power from the power distribution and control relay unit via wires repurposed from control signal wires of the existing garage door button, the user interface including: a wireless communication interface to communicate wirelessly; and a display screen.

Abstract: A processor having a pipelined test access mechanism (TAM). The processor includes a plurality of processor cores. Each of the processor cores includes a scan chain including plurality of serially-coupled scan elements. The processor further includes the pipelined TAM, which includes a plurality of pipeline stages each corresponding to one of the plurality of processor cores. The pipelined TAM includes a command channel, a scan data input (SDI) channel, a scan data output (SDO) channel, and a compare channel. Each pipeline stage is operable to convey commands to its corresponding processor core via the command channel, to convey scan input data to its corresponding processor core via the SDI channel, to receive scan output data conveyed from the corresponding processor core to the SDO channel and the compare channel, and convey compare data downstream via the compare channel, wherein the compare data is based on the scan output data.

Abstract: A processor having a pipelined test access mechanism (TAM). The processor includes a plurality of processor cores. Each of the processor cores includes a scan chain including plurality of serially-coupled scan elements. The processor further includes the pipelined TAM, which includes a plurality of pipeline stages each corresponding to one of the plurality of processor cores. The pipelined TAM includes a command channel, a scan data input (SDI) channel, a scan data output (SDO) channel, and a compare channel. Each pipeline stage is operable to convey commands to its corresponding processor core via the command channel, to convey scan input data to its corresponding processor core via the SDI channel, to receive scan output data conveyed from the corresponding processor core to the SDO channel and the compare channel, and convey compare data downstream via the compare channel, wherein the compare data is based on the scan output data.

Abstract: In one embodiment, an arbiter may provide for opportunistic granting of one or more grants to a requestor that has no available fixed grants remaining in a given arbitration round. In one embodiment, a method may detect that a target resource to be accessed by a requestor with a valid grant count is unavailable during an arbitration round, and opportunistically grant an access grant to another requestor to access a different target resource for a slot of the round. Other embodiments are described and claimed.

Abstract: There is disclosed herein a multi-port frequency step-down queue that efficiently transfers data from a fast clock domain to a slow-clock domain having parallel hardware resources. In one embodiment, the queue includes a set of registers that are sequentially selected by an input counter that receives the fast clock. As the registers are selected, they store a data item from the input data stream. The queue also includes multiple multiplexers each having inputs that are sequentially selected by an output counter that receives the slow clock. The first multiplexer is coupled to the first N registers in the queue, the second multiplexer is coupled to the second N registers in the queue, etc. In this manner, the step-down queue generates multiple output FIFO data streams at the slower clock rate. Each of the output data streams may then be processed in parallel.

Abstract: An adsorption bed arrangement includes a plurality of rigid, shaped adsorption elements within a housing. Each of the shaped adsorption elements includes adsorptive media for removal of chemical contaminants, and preferably includes a binder to retain the adsorptive media in its shape. The adsorption elements are positioned within the housing interior and the housing is selectively openable to provide access to the adsorption elements. A particulate filter, such as with HEPA media, can be included. The particulate filter can be wrapped around a cylindrical rigid shaped adsorption element.

Abstract: An adsorbent article having a base body or matrix onto which is applied an adsorptive coating. The body or matrix can be a honeycomb matrix or structure having a plurality of cells defining a plurality of passages extending through the body. The adsorptive coating comprises an adsorptive media, such as activated carbon or ion exchange resin, that is bound by a polymeric adhesive or resin. A reactant material is preferably included in the adsorptive coating. The adsorbent article has a minimal pressure loss therethrough.

Abstract: An adsorbent article having a base body or matrix onto which is applied an adsorptive coating. The body or matrix can be a honeycomb matrix or structure having a plurality of cells defining a plurality of passages extending through the body. The adsorptive coating comprises an adsorptive media, such as activated carbon or ion exchange resin, that is bound by a polymeric adhesive or resin. The adsorbent article has a minimal pressure loss therethrough.