Abstract: Apparatuses and methods for a timing domain transfer circuit are disclosed. Disclosed embodiments may be configured to receive an event from one timing domain, output the event to another timing domain, and further configured to mark the event as transferred. An example method includes receiving an Event In based in a first timing domain at a first latch and receiving an intermediate event from the first latch by a second latch. The event is transferred to a second timing domain by the second latch and the first latch is reset based on feedback.

Abstract: Apparatuses and methods for a timing domain transfer circuit are disclosed. Disclosed embodiments may be configured to receive an event from one timing domain, output the event to another timing domain, and further configured to mark the event as transferred. An example method includes receiving an Event In based in a first timing domain at a first latch and receiving an intermediate event from the first latch by a second latch. The event is transferred to a second timing domain by the second latch and the first latch is reset based on feedback.

Abstract: Apparatuses and methods for a timing domain transfer circuit are disclosed. Disclosed embodiments may be configured to receive an event from one timing domain, output the event to another timing domain, and further configured to mark the event as transferred. An example method includes receiving an Event in based in a first timing domain at a first latch and receiving an intermediate event from the first latch by a second latch. The event is transferred to a second timing domain by the second latch and the first latch is reset based on feedback.

Abstract: Apparatuses and methods for a timing domain transfer circuit are disclosed. Disclosed embodiments may be configured to receive an event from one timing domain, output the event to another timing domain, and further configured to mark the event as transferred. An example method includes receiving an Event in based in a first timing domain at a first latch and receiving an intermediate event from the first latch by a second latch. The event is transferred to a second timing domain by the second latch and the first latch is reset based on feedback.

Abstract: Apparatuses and methods for a timing domain transfer circuit are disclosed. Disclosed embodiments may be configured to receive an event from one timing domain, output the event to another timing domain, and further configured to mark the event as transferred. An example method includes receiving an Event In based in a first timing domain at a first latch and receiving an intermediate event from the first latch by a second latch. The event is transferred to a second timing domain by the second latch and the first latch is reset based on feedback.

Abstract: A microwavable tray containing a preserved, such as frozen, preferably liquid, food product. The tray can be capable of being folded at least in half and closed after microwaving. The liquid food product contained in the tray has the consistency and texture after microwaving of freshly prepared product, allowing it to be folded at least in half when the tray is folded, or even without a folding tray. During the microwave process, various fillings can be added to the product ether frozen or unfrozen prior to folding.

Abstract: Apparatuses and methods for a timing domain transfer circuit are disclosed. Disclosed embodiments may be configured to receive an event from one timing domain, output the event to another timing domain, and further configured to mark the event as transferred. An example method includes receiving an Event In based in a first timing domain at a first latch and receiving an intermediate event from the first latch by a second latch. The event is transferred to a second timing domain by the second latch and the first latch is reset based on feedback.

Abstract: Methods and apparatuses for shifting data signals are disclosed herein. An apparatus may comprise a clock generation circuit, a delay path, and a driver. The clock generation circuit may be configured to receive an input clock signal and generate a plurality of clock signals based, at least in part, on the clock signal. A delay path may be coupled to the clock generation circuit and configured to receive the input clock signal and the plurality of clock signals. The delay path may be further configured to receive a data signal and delay the data signal based, at least in part, on the input clock signal and each of the plurality of clock signals. A driver may be coupled to the delay path and configured to receive the delayed data signal, and may further be configured to provide the delayed data signal to a bus.

Abstract: Memories and methods for providing and receiving non-data signals at a signal node are disclosed. One such memory includes first and second signal nodes, and first and second signal buffer. The first signal buffer is configured to be operative responsive to a first data strobe signal and further configured to be operative responsive to a non-data signal. The second signal buffer is configured to be operative responsive to a second data strobe signal. An example first data strobe signal is a read data strobe signal provided by the memory. In another example, the first data strobe signal is a write data strobe signal received by the memory. Examples of non-data signals include a data mask signal, data valid signal, error correction signal, as well as other signals.

Abstract: Memories and methods for providing and receiving non-data signals at a signal node are disclosed. One such memory includes first and second signal nodes, and first and second signal buffer. The first signal buffer is configured to be operative responsive to a first data strobe signal and further configured to be operative responsive to a non-data signal. The second signal buffer is configured to be operative responsive to a second data strobe signal. An example first data strobe signal is a read data strobe signal provided by the memory. In another example, the first data strobe signal is a write data strobe signal received by the memory. Examples of non-data signals include a data mask signal, data valid signal, error correction signal, as well as other signals.

Abstract: Cutter blade is a generally elongate member having an undulating portion, a leading edge, a trailing edge, and a width defined by a distance between the leading edge and the trailing edge when viewed from a first side surface. At least a section of the width of the undulating portion located behind the leading edge has a generally uniform thickness. A method of slicing a food product includes mounting at least one cutter blade of any of the types described above on a device that rotates and rotating the at least one cutter about a center axis of the device that rotates. A method of assembling a device for slicing a food product includes mounting at least one cutter blade on a rotating portion of the device.

Abstract: Methods and apparatuses for shifting data signals are disclosed herein. An apparatus may comprise a clock generation circuit, a delay path, and a driver. The clock generation circuit may be configured to receive an input clock signal and generate a plurality of clock signals based, at least in part, on the clock signal. A delay path may be coupled to the clock generation circuit and configured to receive the input clock signal and the plurality of clock signals. The delay path may be further configured to receive a data signal and delay the data signal based, at least in part, on the input clock signal and each of the plurality of clock signals. A driver may be coupled to the delay path and configured to receive the delayed data signal, and may further be configured to provide the delayed data signal to a bus.

Abstract: Methods and devices are disclosed, such as those involving a solid state memory device that includes a status register configured to be read with a combined parallel and serial read scheme. One such solid state memory includes a status register configured to store a plurality of bits indicative of status information of the memory. One such method of providing status information in the memory device includes providing the status information of a memory device in a parallel form. The method also includes providing the status information in a serial form after providing the status information in a parallel form in response to receiving at least one read command.

Abstract: Memories and methods for providing and receiving non-data signals at a signal node are disclosed. One such memory includes first and second signal nodes, and first and second signal buffer. The first signal buffer is configured to be operative responsive to a first data strobe signal and further configured to be operative responsive to a non-data signal. The second signal buffer is configured to be operative responsive to a second data strobe signal. An example first data strobe signal is a read data strobe signal provided by the memory. In another example, the first data strobe signal is a write data strobe signal received by the memory. Examples of non-data signals include a data mask signal, data valid signal, error correction signal, as well as other signals.

Abstract: A trolley capable mining truck includes a pantograph supported on a machine frame for electrically connecting the truck with an overhead trolley line. A power system includes an onboard electrical power source providing electrical power to electric drive propulsion motors along a first electrical path in a first configuration of the power system. The pantograph provides electrical power from the overhead trolley line to the electric drive propulsion motors along a second electrical path, which includes a transient damping reactor, in a second configuration of the power system. The power system also includes a third configuration in which, during a braking mode of the trolley capable mining truck, the electric drive propulsion motors provide regenerative electrical power to the overhead trolley line through the pantograph along a third electrical path including a regenerative power converter, wherein the regenerative power converter includes the transient damping reactor.

Abstract: Methods for improved administration and dosing of DPD inhibitors in combination with 5-FU and/or 5-FU prodrugs are provided, comprising first administering to a patient in need thereof a DPD inhibitor that substantially eliminates activity of the enzyme and thereafter administering 5-FU or a 5-FU prodrug, wherein the level of 5-FU or 5-FU prodrug is in substantial excess of DPD inhibitor in the patient.

Abstract: A trolley capable mining truck includes a pantograph supported on a machine frame for electrically connecting the truck with an overhead trolley line. A power system includes an onboard electrical power source providing electrical power to electric drive propulsion motors along a first electrical path in a first configuration of the power system. The pantograph provides electrical power from the overhead trolley line to the electric drive propulsion motors along a second electrical path, which includes a transient damping reactor, in a second configuration of the power system. The power system also includes a third configuration in which, during a braking mode of the trolley capable mining truck, the electric drive propulsion motors provide regenerative electrical power to the overhead trolley line through the pantograph along a third electrical path including a regenerative power converter, wherein the regenerative power converter includes the transient damping reactor.

Abstract: A trolley capable mining truck includes a pantograph supported on machine frame for electrically connecting the truck with an overhead trolley line. A power system includes an onboard electrical power source providing electrical power to a pair of electric drive propulsion motors along a first electrical path in a first configuration of the power system. The electric drive propulsion motors, in turn, power ground engaging propulsion elements. In a second configuration of the power system, the pantograph provides electrical power from the overhead trolley line to the electric drive propulsion motors along a second electrical path, which includes a transient damping reactor. In a third configuration of the power system, the onboard electrical power source provides electrical power to an auxiliary device along a third electrical path including an auxiliary power converter, wherein the auxiliary power converter includes the transient damping reactor.

Abstract: Methods and devices are disclosed, such as those involving a solid state memory device that includes a status register configured to be read with a combined parallel and serial read scheme. One such solid state memory includes a status register configured to store a plurality of bits indicative of status information of the memory. One such method of providing status information in the memory device includes providing the status information of a memory device in a parallel form. The method also includes providing the status information in a serial form after providing the status information in a parallel form in response to receiving at least one read command.