Patents by Inventor Brian J. Coppa

Brian J. Coppa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11935756
    Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: March 19, 2024
    Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph Neil Greeley, Brian J. Coppa
  • Publication number: 20220254644
    Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
    Type: Application
    Filed: April 27, 2022
    Publication date: August 11, 2022
    Applicant: Micron Technology, Inc.
    Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph Neil Greeley, Brian J. Coppa
  • Patent number: 11335563
    Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: May 17, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph Neil Greeley, Brian J. Coppa
  • Patent number: 11273469
    Abstract: Described herein are architectures, platforms and methods for acquiring optical emission spectra from an optical emission spectroscopy system by flowing a dry cleaning gas into a plasma processing chamber of the plasma processing system and igniting a plasma in the plasma processing chamber to initiate the waferless dry cleaning process.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: March 15, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Brian J. Coppa, Deepak Vedhachalam, Francois C. Dassapa
  • Publication number: 20200406315
    Abstract: Described herein are architectures, platforms and methods for acquiring optical emission spectra from an optical emission spectroscopy system by flowing a dry cleaning gas into a plasma processing chamber of the plasma processing system and igniting a plasma in the plasma processing chamber to initiate the waferless dry cleaning process.
    Type: Application
    Filed: September 11, 2020
    Publication date: December 31, 2020
    Applicant: Tokyo Electron Limited
    Inventors: Brian J. COPPA, Deepak Vedhachalam, Francois C. Dassapa
  • Patent number: 10773282
    Abstract: Described herein are architectures, platforms and methods for acquiring optical emission spectra from an optical emission spectroscopy system by flowing a dry cleaning gas into a plasma processing chamber of the plasma processing system and igniting a plasma in the plasma processing chamber to initiate the waferless dry cleaning process.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: September 15, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Brian J. Coppa, Deepak Vedhachalam, Francois C. Dassapa
  • Publication number: 20200203171
    Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
    Type: Application
    Filed: March 2, 2020
    Publication date: June 25, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph Neil Greeley, Brian J. Coppa
  • Patent number: 10607844
    Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: March 31, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph Neil Greeley, Brian J. Coppa
  • Patent number: 10446453
    Abstract: A method is disclosed for monitoring and controlling a process of plasma-assisted surface modification of a layer formed on a substrate. The method includes flowing a surface modification gas into a plasma processing chamber of a plasma processing system, igniting a plasma in the plasma processing chamber to initiate a surface modification process for a layer formed on a substrate, and acquiring optical emission spectra from an optical emission spectroscopy system attached to the plasma processing chamber, during the surface modification process for the layer. For one embodiment, the method includes altering at least one parameter of the surface modification process based on the acquired optical emission spectra. For one embodiment, the acquired optical emission spectra can include an intensity of a spectral line, a slope of a spectral line, or both to enable endpoint control of the surface modification process. Additional methods and related systems are also disclosed.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: October 15, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Brian J. Coppa, Viswas Purohit, Seiichi Watanabe, Kenji Komatsu
  • Patent number: 10333047
    Abstract: Electrical, mechanical, computing, and/or other devices that include components formed of extremely low resistance (ELR) materials, including, but not limited to, modified ELR materials, layered ELR materials, and new ELR materials, are described.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: June 25, 2019
    Assignee: Ambatrue, Inc.
    Inventors: Douglas J. Gilbert, Y. Eugene Shteyn, Michael J. Smith, Joel Patrick Hanna, Paul Greenland, Brian J. Coppa, Forrest J. North
  • Patent number: 10304668
    Abstract: Plasma processing conditions may be changed for localized regions of a substrate. A reactive gas may be maintained in a localized region of a substrate while other regions of the substrate are not exposed to the reactive gas. Thus, plasma conditions may be generated at specific regions of the substrate. A multi-zoned gas injection system may be utilized to direct certain gases in certain regions of the plasma space. Techniques may be provided to maintain these gases in the desired regions, as opposed to the gases spreading across the substrate surface. Reactive gases may be provided in one region while a flow of inert gas is provided in other regions in which it is desired to restrict the effects of the reactive gases. Localized control of the plasma process may be provided as a separate plasma processing step. The localized region of the substrate may be the substrate edge.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: May 28, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Brian J. Coppa, Vaidya Bharadwaj
  • Patent number: 10096483
    Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: October 9, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph Neil Greeley, Brian J. Coppa
  • Publication number: 20180286693
    Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
    Type: Application
    Filed: May 30, 2018
    Publication date: October 4, 2018
    Applicant: Micron Technology, Inc.
    Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph Neil Greeley, Brian J. Coppa
  • Publication number: 20180269119
    Abstract: A method is disclosed for monitoring and controlling a process of plasma-assisted surface modification of a layer formed on a substrate. The method includes flowing a surface modification gas into a plasma processing chamber of a plasma processing system, igniting a plasma in the plasma processing chamber to initiate a surface modification process for a layer formed on a substrate, and acquiring optical emission spectra from an optical emission spectroscopy system attached to the plasma processing chamber, during the surface modification process for the layer. For one embodiment, the method includes altering at least one parameter of the surface modification process based on the acquired optical emission spectra. For one embodiment, the acquired optical emission spectra can include an intensity of a spectral line, a slope of a spectral line, or both to enable endpoint control of the surface modification process. Additional methods and related systems are also disclosed.
    Type: Application
    Filed: March 13, 2018
    Publication date: September 20, 2018
    Inventors: Brian J. Coppa, Viswas Purohit
  • Publication number: 20170372913
    Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
    Type: Application
    Filed: August 18, 2017
    Publication date: December 28, 2017
    Applicant: Micron Technology, Inc.
    Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph Neil Greeley, Brian J. Coppa
  • Publication number: 20170345626
    Abstract: Plasma processing conditions may be changed for localized regions of a substrate. A reactive gas may be maintained in a localized region of a substrate while other regions of the substrate are not exposed to the reactive gas. Thus, plasma conditions may be generated at specific regions of the substrate. A multi-zoned gas injection system may be utilized to direct certain gases in certain regions of the plasma space. Techniques may be provided to maintain these gases in the desired regions, as opposed to the gases spreading across the substrate surface. Reactive gases may be provided in one region while a flow of inert gas is provided in other regions in which it is desired to restrict the effects of the reactive gases. Localized control of the plasma process may be provided as a separate plasma processing step. The localized region of the substrate may be the substrate edge.
    Type: Application
    Filed: May 11, 2017
    Publication date: November 30, 2017
    Inventors: Brian J. Coppa, Vaidya Bharadwaj
  • Publication number: 20170282223
    Abstract: Described herein are architectures, platforms and methods for acquiring optical emission spectra from an optical emission spectroscopy system by flowing a dry cleaning gas into a plasma processing chamber of the plasma processing system and igniting a plasma in the plasma processing chamber to initiate the waferless dry cleaning process.
    Type: Application
    Filed: March 24, 2017
    Publication date: October 5, 2017
    Inventors: Brian J. Coppa, Deepak Vedhachalam, Francois C. Dassapa
  • Publication number: 20170287791
    Abstract: Described herein are architectures, platforms and methods for acquiring optical emission spectra from an optical emission spectroscopy system by flowing a dry cleaning gas into a plasma processing chamber of the plasma processing system and igniting a plasma in the plasma processing chamber to initiate the waferless dry cleaning process.
    Type: Application
    Filed: March 24, 2017
    Publication date: October 5, 2017
    Inventors: Brian J. Coppa, Deepak Vedhachalam, Francois C. Dassapa
  • Patent number: 9761457
    Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: September 12, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph Neil Greeley, Brian J. Coppa
  • Publication number: 20160203993
    Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
    Type: Application
    Filed: March 21, 2016
    Publication date: July 14, 2016
    Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph Neil Greeley, Brian J. Coppa