Patents by Inventor Brian J. Coppa

Brian J. Coppa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10446453
    Abstract: A method is disclosed for monitoring and controlling a process of plasma-assisted surface modification of a layer formed on a substrate. The method includes flowing a surface modification gas into a plasma processing chamber of a plasma processing system, igniting a plasma in the plasma processing chamber to initiate a surface modification process for a layer formed on a substrate, and acquiring optical emission spectra from an optical emission spectroscopy system attached to the plasma processing chamber, during the surface modification process for the layer. For one embodiment, the method includes altering at least one parameter of the surface modification process based on the acquired optical emission spectra. For one embodiment, the acquired optical emission spectra can include an intensity of a spectral line, a slope of a spectral line, or both to enable endpoint control of the surface modification process. Additional methods and related systems are also disclosed.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: October 15, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Brian J. Coppa, Viswas Purohit, Seiichi Watanabe, Kenji Komatsu
  • Patent number: 10333047
    Abstract: Electrical, mechanical, computing, and/or other devices that include components formed of extremely low resistance (ELR) materials, including, but not limited to, modified ELR materials, layered ELR materials, and new ELR materials, are described.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: June 25, 2019
    Assignee: Ambatrue, Inc.
    Inventors: Douglas J. Gilbert, Y. Eugene Shteyn, Michael J. Smith, Joel Patrick Hanna, Paul Greenland, Brian J. Coppa, Forrest J. North
  • Patent number: 10304668
    Abstract: Plasma processing conditions may be changed for localized regions of a substrate. A reactive gas may be maintained in a localized region of a substrate while other regions of the substrate are not exposed to the reactive gas. Thus, plasma conditions may be generated at specific regions of the substrate. A multi-zoned gas injection system may be utilized to direct certain gases in certain regions of the plasma space. Techniques may be provided to maintain these gases in the desired regions, as opposed to the gases spreading across the substrate surface. Reactive gases may be provided in one region while a flow of inert gas is provided in other regions in which it is desired to restrict the effects of the reactive gases. Localized control of the plasma process may be provided as a separate plasma processing step. The localized region of the substrate may be the substrate edge.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: May 28, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Brian J. Coppa, Vaidya Bharadwaj
  • Patent number: 10096483
    Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: October 9, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph Neil Greeley, Brian J. Coppa
  • Publication number: 20180286693
    Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
    Type: Application
    Filed: May 30, 2018
    Publication date: October 4, 2018
    Applicant: Micron Technology, Inc.
    Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph Neil Greeley, Brian J. Coppa
  • Publication number: 20180269119
    Abstract: A method is disclosed for monitoring and controlling a process of plasma-assisted surface modification of a layer formed on a substrate. The method includes flowing a surface modification gas into a plasma processing chamber of a plasma processing system, igniting a plasma in the plasma processing chamber to initiate a surface modification process for a layer formed on a substrate, and acquiring optical emission spectra from an optical emission spectroscopy system attached to the plasma processing chamber, during the surface modification process for the layer. For one embodiment, the method includes altering at least one parameter of the surface modification process based on the acquired optical emission spectra. For one embodiment, the acquired optical emission spectra can include an intensity of a spectral line, a slope of a spectral line, or both to enable endpoint control of the surface modification process. Additional methods and related systems are also disclosed.
    Type: Application
    Filed: March 13, 2018
    Publication date: September 20, 2018
    Inventors: Brian J. Coppa, Viswas Purohit
  • Publication number: 20170372913
    Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
    Type: Application
    Filed: August 18, 2017
    Publication date: December 28, 2017
    Applicant: Micron Technology, Inc.
    Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph Neil Greeley, Brian J. Coppa
  • Publication number: 20170345626
    Abstract: Plasma processing conditions may be changed for localized regions of a substrate. A reactive gas may be maintained in a localized region of a substrate while other regions of the substrate are not exposed to the reactive gas. Thus, plasma conditions may be generated at specific regions of the substrate. A multi-zoned gas injection system may be utilized to direct certain gases in certain regions of the plasma space. Techniques may be provided to maintain these gases in the desired regions, as opposed to the gases spreading across the substrate surface. Reactive gases may be provided in one region while a flow of inert gas is provided in other regions in which it is desired to restrict the effects of the reactive gases. Localized control of the plasma process may be provided as a separate plasma processing step. The localized region of the substrate may be the substrate edge.
    Type: Application
    Filed: May 11, 2017
    Publication date: November 30, 2017
    Inventors: Brian J. Coppa, Vaidya Bharadwaj
  • Publication number: 20170287791
    Abstract: Described herein are architectures, platforms and methods for acquiring optical emission spectra from an optical emission spectroscopy system by flowing a dry cleaning gas into a plasma processing chamber of the plasma processing system and igniting a plasma in the plasma processing chamber to initiate the waferless dry cleaning process.
    Type: Application
    Filed: March 24, 2017
    Publication date: October 5, 2017
    Inventors: Brian J. Coppa, Deepak Vedhachalam, Francois C. Dassapa
  • Publication number: 20170282223
    Abstract: Described herein are architectures, platforms and methods for acquiring optical emission spectra from an optical emission spectroscopy system by flowing a dry cleaning gas into a plasma processing chamber of the plasma processing system and igniting a plasma in the plasma processing chamber to initiate the waferless dry cleaning process.
    Type: Application
    Filed: March 24, 2017
    Publication date: October 5, 2017
    Inventors: Brian J. Coppa, Deepak Vedhachalam, Francois C. Dassapa
  • Patent number: 9761457
    Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: September 12, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph Neil Greeley, Brian J. Coppa
  • Publication number: 20160203993
    Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
    Type: Application
    Filed: March 21, 2016
    Publication date: July 14, 2016
    Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph Neil Greeley, Brian J. Coppa
  • Patent number: 9305782
    Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: April 5, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph Neil Greely, Brian J. Coppa
  • Publication number: 20150021744
    Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
    Type: Application
    Filed: October 6, 2014
    Publication date: January 22, 2015
    Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph Neil Greely, Brian J. Coppa
  • Patent number: 8852851
    Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
    Type: Grant
    Filed: July 10, 2006
    Date of Patent: October 7, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph N. Greeley, Brian J. Coppa
  • Publication number: 20140113828
    Abstract: Electrical, mechanical, computing, and/or other devices that include components formed of extremely low resistance (ELR) materials, including, but not limited to, modified ELR materials, layered ELR materials, and new ELR materials, are described.
    Type: Application
    Filed: March 30, 2012
    Publication date: April 24, 2014
    Applicant: AMBATURE INC.
    Inventors: Douglas J. Gilbert, Y. Eugene Shteyn, Michael J. Smith, Joel Patrick Hanna, Paul Greenland, Brian J. Coppa, Forrest J. North
  • Patent number: 8129289
    Abstract: Methods of controlling critical dimensions of reduced-sized features during semiconductor fabrication through pitch multiplication are disclosed. Pitch multiplication is accomplished by patterning mask structures via conventional photoresist techniques and subsequently transferring the pattern to a sacrificial material. Spacer regions are then formed on the vertical surfaces of the transferred pattern following the deposition of a conformal material via atomic layer deposition. The spacer regions, and therefore the reduced features, are then transferred to a semiconductor substrate.
    Type: Grant
    Filed: October 5, 2006
    Date of Patent: March 6, 2012
    Assignee: Micron Technology, Inc.
    Inventors: John A. Smythe, Gurtej S. Sandhu, Brian J. Coppa, Shyam Surthi, Shuang Meng
  • Publication number: 20080179715
    Abstract: A method for providing an isolation material, for example trench isolation for a semiconductor device, comprises forming a first dielectric such as silicon dioxide using an atomic layer deposition (ALD) process within a trench, partially etching the first dielectric, then forming a second dielectric such as a silicon dioxide using a high density plasma (HDP) deposition within the trench. The second dielectric provides desirable properties such as resistance to specific etches than the first dielectric, while the first dielectric fills high aspect ratio openings more easily than the second dielectric. Depositing the first dielectric results in a decreased trench aspect ratio which must be filled by the second dielectric.
    Type: Application
    Filed: January 30, 2007
    Publication date: July 31, 2008
    Inventor: Brian J. Coppa
  • Publication number: 20080085612
    Abstract: Methods of controlling critical dimensions of reduced-sized features during semiconductor fabrication through pitch multiplication are disclosed. Pitch multiplication is accomplished by patterning mask structures via conventional photoresist techniques and subsequently transferring the pattern to a sacrificial material. Spacer regions are then formed on the vertical surfaces of the transferred pattern following the deposition of a conformal material via atomic layer deposition. The spacer regions, and therefore the reduced features, are then transferred to a semiconductor substrate.
    Type: Application
    Filed: October 5, 2006
    Publication date: April 10, 2008
    Inventors: John A. Smythe, Gurtej S. Sandhu, Brian J. Coppa, Shyam Surthi, Shuang Meng
  • Publication number: 20080008969
    Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
    Type: Application
    Filed: July 10, 2006
    Publication date: January 10, 2008
    Inventors: Baosuo Zhou, Mirzafer K. Abatchev, Ardavan Niroomand, Paul A. Morgan, Shuang Meng, Joseph N. Greeley, Brian J. Coppa