Abstract: A first hypervisor running on a first processor cluster is provided. During operation, the first hypervisor can determine a first set of processing nodes and a first memory unit of the first processor cluster in response to the booting up of a first Basic Input/Output System (BIOS) of the first processor cluster. The first hypervisor can discover a second hypervisor running on a second processor cluster comprising a second set of processing nodes and a second memory unit. The first hypervisor can operate, with the second hypervisor, a distributed system comprising the first and second sets of processing nodes and the first and second memory units. The first hypervisor can then operate, with the second hypervisor, a global virtual machine on the distributed system. The virtual memory space of the global virtual machine can be mapped to respective memory spaces of the first and second processor clusters.

Abstract: One aspect of the application can provide a system and method for replacing a failing node with a spare node in a non-uniform memory access (NUMA) system. During operation, in response to determining that a node-migration condition is met, the system can initialize a node controller of the spare node such that accesses to a memory local to the spare node are to be processed by the node controller, quiesce the failing node and the spare node to allow state information of processors on the failing node to be migrated to processors on the spare node, and subsequent to unquiescing the failing node and the spare node, migrate data from the failing node to the spare node while maintaining cache coherence in the NUMA system and while the NUMA system remains in operation, thereby facilitating continuous execution of processes previously executed on the failing node.

Abstract: A first hypervisor running on a first processor cluster is provided. During operation, the first hypervisor can determine a first set of processing nodes and a first memory unit of the first processor cluster in response to the booting up of a first Basic Input/Output System (BIOS) of the first processor cluster. The first hypervisor can discover a second hypervisor running on a second processor cluster comprising a second set of processing nodes and a second memory unit. The first hypervisor can operate, with the second hypervisor, a distributed system comprising the first and second sets of processing nodes and the first and second memory units. The first hypervisor can then operate, with the second hypervisor, a global virtual machine on the distributed system. The virtual memory space of the global virtual machine can be mapped to respective memory spaces of the first and second processor clusters.

Abstract: One aspect of the application can provide a system and method for replacing a failing node with a spare node in a non-uniform memory access (NUMA) system. During operation, in response to determining that a node-migration condition is met, the system can initialize a node controller of the spare node such that accesses to a memory local to the spare node are to be processed by the node controller, quiesce the failing node and the spare node to allow state information of processors on the failing node to be migrated to processors on the spare node, and subsequent to unquiescing the failing node and the spare node, migrate data from the failing node to the spare node while maintaining cache coherence in the NUMA system and while the NUMA system remains in operation, thereby facilitating continuous execution of processes previously executed on the failing node.

Abstract: A multi-functional water quality sensor assembly includes an electrically non-conductive substrate carrying electrically conductive traces that comprise one or more electrodes configured to sense at least one of oxidation reduction potential (ORP) or acidity (pH) of water. The electrodes are configured to be operated according to a dynamic mode, which includes establishing constant potentials or constant currents between the electrodes and documenting potentials between the electrodes as a measure of ORP and/or pH, and/or determining a differential in the potentials between first and second times as a measure of pH of the water, wherein the dynamic mode may be carried out without use of a silver chloride reference electrode.

Abstract: A multi-functional sensor assembly includes an electrically non-conductive substrate defining at least a distal region, intermediary region, and proximal region that are each covered with electrically conductive traces. The proximal region is configured to be exposed to a media to be sensed and the distal and intermediary regions are configured to be protected from the media. The electrically conductive traces comprise at least electrical circuits to sense temperature and flow of the media and one or more electrodes to sense one or more of conductivity, oxidation reduction potential (ORP), and acidity (pH) of the media.

Abstract: A high performance computing system and methods are disclosed. The system includes logical partitions with physically removable nodes that each have at least one processor, and memory that can be shared with other nodes. Node hardware may be removed or allocated to another partition without a reboot or power cycle. Memory sharing is tracked using a memory directory. Cache coherence operations on the memory directory include a test to determine whether a given remote node has been removed. If the remote node is not present, system hardware simulates a valid response from the missing node.

Abstract: A multi-functional sensor assembly includes an electrically non-conductive substrate defining at least a distal region, intermediary region, and proximal region that are each covered with electrically conductive traces. The proximal region is configured to be exposed to a media to be sensed and the distal and intermediary regions are configured to be protected from the media. The electrically conductive traces comprise at least electrical circuits to sense temperature and flow of the media and one or more electrodes to sense one or more of conductivity, oxidation reduction potential (ORP), and acidity (pH) of the media.

Abstract: A nitric oxide delivery system can include a cassette which is a single use disposable component used to store liquid N2O4, activate upon operator demand, convert N2O4 to NO2 via a heating element(s) controlled by a console to deliver NO2 at a controlled flow rate, direct concentrated NO2 to a contained pair of conversion cartridges and exhaust NO gas to the console for delivery to the patient.

Abstract: Processor clock signals are generated for each processor in a HPC system, such that all the processor clock signals are of the same frequency. Furthermore, as part of a startup (boot) procedure, a process sets all time stamp counters (TSCs) of the processors, such they indicate identical times. Each blade of the HPC system recovers a recovered clock signal from a synchronous communication network, to which the blade is coupled. The blade generates a processor clock from the recovered clock signal and provides the processor clock to processor(s) on the blade. Each chassis is coupled to a second, system-wide, synchronous communication network, and each chassis synchronizes its chassis synchronous communication network with the system-wide synchronous communication system. Thus, all the processor clock signals are generated with the same frequency.

Abstract: Processor clock signals are generated for each processor in a HPC system, such that all the processor clock signals are of the same frequency. Furthermore, as part of a startup (boot) procedure, a process sets all time stamp counters (TSCs) of the processors, such they indicate identical times. Each blade of the HPC system recovers a recovered clock signal from a synchronous communication network, to which the blade is coupled. The blade generates a processor clock from the recovered clock signal and provides the processor clock to processor(s) on the blade. Each chassis is coupled to a second, system-wide, synchronous communication network, and each chassis synchronizes its chassis synchronous communication network with the system-wide synchronous communication system. Thus, all the processor clock signals are generated with the same frequency.

Abstract: A high performance computing system and methods are disclosed. The system includes logical partitions with physically removable nodes that each have at least one processor, and memory that can be shared with other nodes. Node hardware may be removed or allocated to another partition without a reboot or power cycle. Memory sharing is tracked using a memory directory. Cache coherence operations on the memory directory include a test to determine whether a given remote node has been removed. If the remote node is not present, system hardware simulates a valid response from the missing node.

Abstract: A method for efficiently treating wastewater by aerobic digestion whereby on-site oxygen generating equipment continually provides a predetermined quantity of dissolved oxygen to the wastewater, the dissolved oxygen content being maintained at a predetermined level during peak flows by air being dissolved into the wastewater. The method being used for upgrading the capacity of an existing plant to treat wastewater; increasing the scope of an existing plant to allow removal of biological nitrogen and/or phosphorus; and designing new wastewater treatment plants. Further efficiency is introduced by using methane produced, during subsequent anaerobic digestion of the wastewater, to fuel compressors or the like which provide the air to the wastewater.