Abstract: Methods and digital circuits provide frequency correction to frequency synthesizers. Dual switched-capacitor voltage detectors connected to an input signal periodically sample the voltage of the input signal, and then determine a fundamental frequency of the input signal from the output of the dual switched-capacitor voltage detectors. The sample period of the dual switched-capacitor voltage detectors is proportional to a time period between a previous pair of voltage peaks detected in the input signal, thereby eliminating harmonic components in the original signal which might otherwise cause errors in frequency estimation without causing unwanted sluggishness in the transient response of the frequency detection process. The time period between the previous pair of detected voltage peaks is used to create a decay signal that initiates a capacitor decay time for each voltage detector.

Abstract: Controlling power consumption in a wireless device. The wireless device may include first wireless protocol circuitry. The first wireless protocol circuitry may be configured to receive and process first signals according to a first wireless protocol. The wireless device may include a power controller coupled to the first wireless protocol circuitry. The power controller may be configured to control power consumption of elements of the first wireless protocol circuitry based on a current state. More specifically, in response to the first wireless protocol circuitry being in a listening state, the power controller may be configured to lower power consumption of one or more first elements of the first wireless protocol circuitry. Additionally, in response to the first wireless protocol circuitry being in a receiving state, the power controller may be configured to return power consumption of the one or more first elements to a higher power level.

Abstract: Controlling power consumption in a wireless device. The wireless device may include first wireless protocol circuitry. The first wireless protocol circuitry may be configured to receive and process first signals according to a first wireless protocol. The wireless device may include a power controller coupled to the first wireless protocol circuitry. The power controller may be configured to control power consumption of elements of the first wireless protocol circuitry based on a current state. More specifically, in response to the first wireless protocol circuitry being in a listening state, the power controller may be configured to lower power consumption of one or more first elements of the first wireless protocol circuitry. Additionally, in response to the first wireless protocol circuitry being in a receiving state, the power controller may be configured to return power consumption of the one or more first elements to a higher power level.

Abstract: This invention relates to effects processing of a monophonic analog signal, meaning a signal whose frequency components are all integer multiples of a first fundamental frequency. For example, the signal could come from almost any musical instrument, voice included. However, for generality, the invention is not restricted to cases where the signal source is musical. The digital signal processing is simplified as a result of the DSP being clocked at a constant multiple of ffund. This means that the sine and cosine functions, as well as the low-pass filters which make up each harmonic selector, are trivial to implement because the frequencies of each sine/cosine, as well as the cutoff frequency of the low-pass filters, are constant fractions of the DSP clock frequency.

Abstract: A timing circuit for generating asynchronous signals is provided that uses minimal area while maximizing speed. This timing circuit can include a timing control block and disable/enable circuitry. The timing control block can include an SR latch and first and second delay blocks. The SR latch can generate first and second signals, wherein the first and second signals are asynchronous. The first delay block can generate a delayed first signal and provide that signal to a first input terminal of the SR latch. Similarly, the second delay block can generate a delayed second signal and provide that signal to a second input terminal of the SR latch. Notably, the first and second delay blocks delay positive going edges of the first and second signals differently than negative going edges of the first and second signals.

Abstract: A method of designing stacked circuits for an integrated circuit is described. In this method, a plurality of devices that are stackable may be determined. Some of those devices, i.e. a subset of stackable devices, may be formed in a deep n-well, thereby allowing that subset of stackable devices to receive an increased supply voltage. The remainder of the stackable devices may be formed in a standard n-well, thereby allowing such devices to receive a standard supply voltage. In one embodiment, the standard supply voltage may be VDD and the increased supply voltage may be 2×VDD. This method may be advantageously used in both the design of stacked circuits for and the implementation of stacked circuits in an integrated circuit.

Abstract: An RF coupling circuit including a transformer and a parallel AC-coupling capacitor can advantageously ameliorate substantial attenuation of a signal, prevent destabilization of any feedback loop, and simplify the circuit design process. The AC-coupling capacitor can act as an “averager”, i.e. both the input and output sides of coupling circuit represent capacitances equal to the average of the input and the output capacitances. Thus, the inductors for tuning them out can become equal, thereby allowing a symmetric (or near symmetric) transformer to be used in the RF coupling circuit. When tuned properly, the transformer plus AC-coupling capacitor can also advantageously provide better in-band gain as well as frequency selectivity than other conventional coupling circuits.

Abstract: This invention relates to effects processing of a monophonic analog signal, meaning a signal whose frequency components are all integer multiples of a first fundamental frequency. For example, the signal could come from almost any musical instrument, voice included. However, for generality, the invention is not restricted to cases where the signal source is musical. The digital signal processing is simplified as a result of the DSP being clocked at a constant multiple of ffund. This means that the sine and cosine functions, as well as the low-pass filters which make up each harmonic selector, are trivial to implement because the frequencies of each sine/cosine, as well as the cutoff frequency of the low-pass filters, are constant fractions of the DSP clock frequency.

Abstract: A method and apparatus are disclosed for clocking a DSP at a frequency which is always a constant integer multiple of the fundamental frequency of the input analog signal. This invention applies in situations where the analog signal exhibits certain characteristics in which a fixed clock frequency is not desired, but rather what is needed is a clock which tracks the fundamental frequency of the analog signal, for example, a signal from a monophonic musical instrument or a polyphonic instrument being played one note at a time.

Abstract: A transceiver includes a power control circuit in the transmitter that operates on a packet-by-packet basis. The transceiver can, for each packet, set a variable gain amplifier to a first gain and use predetermined gain increments to thereafter increase gain until a gain hold event. The gain hold event can be an expiration of a time duration allocated for changing gain or a desired power being reached, whichever event occurs first. The gain can be adjusted by a predetermined amount based on an operating condition.

Abstract: The present invention includes a transceiver and a method of operating the same that includes in the transmitter a power control circuit that operates on an analog differential signal containing data packets individually. The power control circuit initially transmits a series of data symbols with known values, periodically strobes the transceiver system for correct power levels and incrementally increases the power level of the transceiver until the optimal gain is reached, without exceeding the maximum output power.

Abstract: The present invention includes a transceiver and a method of operating the same that includes in the transmitter a power control circuit that operates on an analog differential signal containing data packets individually. The power control circuit initially transmits a series of data symbols with known values, periodically strobes the transceiver system for correct power levels and incrementally increases the power level of the transceiver until the optimal gain is reached, without exceeding the maximum output power.

Abstract: The present invention includes a transceiver and a method of operating the same that includes in the transmitter a power control circuit that operates on an analog differential signal containing data packets individually. The power control circuit initially transmits a series of data symbols with known values, periodically strobes the transceiver system for correct power levels and incrementally increases the power level of the transceiver until the optimal gain is reached, without exceeding the maximum output power.