Abstract: A multi-phase clock generator has a set of transistors, a first latch, and a second latch. The set of transistors may be arranged in a sense amplifier latch architecture, in which the set of transistors include a first inverter and a second inverter. The first inverter may provide a first phase data strobe signal and the second inverter may provide a second phase data strobe signal. The first latch and the second latch are coupled to the set of transistors. The set of transistors may receive a first portion of current at the first inverter and a second portion of current at the second inverter. The set of transistors may amplify the first portion of current in response to the first portion being greater than the second portion. The set of transistors may also drive the first phase data strobe signal using the amplified first portion.

Abstract: A multi-phase clock generator has a set of transistors, a first latch, and a second latch. The set of transistors may be arranged in a sense amplifier latch architecture, in which the set of transistors include a first inverter and a second inverter. The first inverter may provide a first phase data strobe signal and the second inverter may provide a second phase data strobe signal. The first latch and the second latch are coupled to the set of transistors. The set of transistors may receive a first portion of current at the first inverter and a second portion of current at the second inverter. The set of transistors may amplify the first portion of current in response to the first portion being greater than the second portion. The set of transistors may also drive the first phase data strobe signal using the amplified first portion.

Abstract: Systems and methods may involve circuitry that receives a first transition of a clocking signal. The circuitry may also to enable a compensation circuit characterized by a capacitance in response to the first transition of the clocking signal and may receive subsequent transitions of the clocking signal. The circuitry may also apply the capacitance to the subsequent transitions of the clocking signal after enabling the compensation circuit to generate a compensated clocking signal characterized by an adjusted duty cycle relative to a duty cycle of the clocking signal.

Abstract: A method, apparatus, and system are provided for implementing a zero-enabled fuse system. An apparatus includes a first set of fuses for activating a first memory portion, and a second set of fuses for activating a second memory portion. The apparatus also includes a controller to control an operation of the first and second set of fuses. The controller is adapted to determine whether a zero address memory location relating to the first memory portion is to be activated based upon an enable fuse. The controller is adapted to also perform a check to determine whether the second set of fuses has been previously activated.

Abstract: A method, apparatus, and system are provided for implementing a zero-enabled fuse system. An apparatus includes a first set of fuses for activating a first memory portion, and a second set of fuses for activating a second memory portion. The apparatus also includes a controller to control an operation of the first and second set of fuses. The controller is adapted to determine whether a zero address memory location relating to the first memory portion is to be activated based upon an enable fuse. The controller is adapted to also perform a check to determine whether the second set of fuses has been previously activated.

Abstract: A method and apparatus for programmable column segmentation of a memory device is disclosed. The method and apparatus provide different programmable selected column segmentation arrangements to provide more flexibility in primary column repair of a memory device.

Abstract: A method and apparatus for programmable column segmentation of a memory device is disclosed. The method and apparatus provide different programmable selected column segmentation arrangements to provide more flexibility in primary column repair of a memory device.

Abstract: A method and apparatus for programmable column segmentation of a memory device is disclosed. The method and apparatus provide different programmable selected column segmentation arrangements to provide more flexibility in primary column repair of a memory device.

Abstract: A method and apparatus for programmable column segmentation of a memory device is disclosed. The method and apparatus provide different programmable selected column segmentation arrangements to provide more flexibility in primary column repair of a memory device.