Abstract: This disclosure describes a design tool that verifies timing of an integrated circuit design by partitioning the integrated circuit design's gate-level netlist into target cell partition netlists and performs transistor-level circuit simulation on each target cell partition netlist. The design tool performs a back tracing procedure on each target sequential cell to define the target cell partition netlists. The design tool then identifies timing modes that enable valid logical paths through the target cell partition netlists from source sequential cells to the target sequential cells. In turn, the design tool performs transistor-level circuit simulation (e.g., SPICE simulations) on each target cell partition netlist to check for timing violations based upon the timing modes.

Abstract: This disclosure describes a design tool that verifies timing of an integrated circuit design by partitioning the integrated circuit design's gate-level netlist into target cell partition netlists and performs transistor-level circuit simulation on each target cell partition netlist. The design tool performs a back tracing procedure on each target sequential cell to define the target cell partition netlists. The design tool then identifies timing modes that enable valid logical paths through the target cell partition netlists from source sequential cells to the target sequential cells. In turn, the design tool performs transistor-level circuit simulation (e.g., SPICE simulations) on each target cell partition netlist to check for timing violations based upon the timing modes.

Abstract: A method and apparatus for simulating the design of an integrated circuit uses a processor (200). The processor (200) executes a simulator (540) from memory (280) to exercise a model (544). The data points (15-27) of an output signal are stored in a history data file (542). The techniques used to generate each of the data points (15-27) are also stored in the history data in file (542). The history data are then used to generate a converted output signal that has a uniform time scale. If the converted output signal requires the generation of a desired data point, then the approximation technique used to generate the following data point stored in the history data (542) is used.