Abstract: A microprogram controlled data processing apparatus is described, in which each machine-level instruction is divided into a number of phases, and each phase is executed by a sequence of microinstructions. The machine-level instruction is decoded to produce a set of microprogram parameters, and in each phase of the instruction a sub-set of these parameters is selected, and broadcast over a parameter bus to individual decoders which decode the microinstructions, so as to qualify the effects of the microinstructions. The use of parameters in this way allows the same microprogram sequence to be used for several different instruction variants, and hence reduces the total size of the microprogram.

Abstract: A data processing system consists of a number of modules such as integrated circuit chips, each of which receives a clock signal. Each module contains a checking circuit producing a failure signal which indicates whether or not the module is operating correctly. The clock signal is used to invert the sense of this failure signal in successive clock periods. Thus, the failure signal normally alternates between two values in successive clock periods, and its phase relative to the clock signal denotes whether or not a failure has been detected. However, if the clock supply to a module fails, or if the checking circuit itself fails, the failure signal from that module no longer alternates, but is frozen at one or other of the two values. This allows failure of the clock supply or of the checking circuit to be detected.

Abstract: A data processing system is disclosed in which a store has a plurality of pairs of storage locations. An indicator is provided for each location pair to indicate which location of the pairs is to be used for read and write accesses. The indicators are each set to indicate that after a write access to a pair of locations, read accesses are to take place to the location of the pair currently indicated for write accesses and periodically, for example at the end of a sequence of instructions, the indicators are set to indicate that write accesses are to take place to the opposite location of the pair to that which is currently indicated for read accesses.