Patents by Inventor Brian J. Sandvold

Brian J. Sandvold has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Standardized test board for testing custom chips
    Patent number: 6430047
    Abstract: A printed wiring board provides connection between a chip and a standard footprint layout of a test machine. An insulating substrate defines a chip receiving region having a plurality of chip connector pads on one side of the substrate for connection to bump contacts of custom integrated circuit chips. A plurality of layout connectors are in a layout connection region of the board and arranged in the standard footprint layout. Circuit traces provide electrical connection between the chip connectors and the layout connectors, and a solder stop on the substrate extends over the circuit traces between the chip receiving region and the layout connection region. A plurality of plated apertures extend through the substrate in the chip receiving region to a thermally conductive heat sink opposite the chip connectors. In use, a chip is mounted to the board in the chip receiving region and connected to the chip connectors to rigidly mount the chip to the board.
    Type: Grant
    Filed: October 4, 1999
    Date of Patent: August 6, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Earl E. Wentzel, Brant R. Gourley, Gregory A. King, Paul F. Cisewski, Steven V. Stang, Gregory P. Micko, Brian J. Sandvold
  • STANDARDIZED TEST BOARD FOR TESTING CUSTOM CHIPS
    Publication number: 20020001179
    Abstract: A printed wiring board provides connection between a chip and a standard footprint layout of a test machine. An insulating substrate defines a chip receiving region having a plurality of chip connector pads on one side of the substrate for connection to bump contacts of custom integrated circuit chips. A plurality of layout connectors are in a layout connection region of the board and arranged in the standard footprint layout. Circuit traces provide electrical connection between the chip connectors and the layout connectors, and a solder stop on the substrate extends over the circuit traces between the chip receiving region and the layout connection region. A plurality of plated apertures extend through the substrate in the chip receiving region to a thermally conductive heat sink opposite the chip connectors. In use, a chip is mounted to the board in the chip receiving region and connected to the chip connectors to rigidly mount the chip to the board.
    Type: Application
    Filed: October 4, 1999
    Publication date: January 3, 2002
    Inventors: EARL E. WENTZEL, BRANT R. GOURLEY, GREGORY A. KING, PAUL F. CISEWSKI, STEVEN V. STANG, GREGORY P. MICKO, BRIAN J. SANDVOLD