Patents by Inventor Brian J. Slechta

Brian J. Slechta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11609859
    Abstract: Embodiments of the invention include a machine-readable medium having stored thereon at least one instruction, which if performed by a machine causes the machine to perform a method that includes decoding, with a node, an invalidate instruction; and executing, with the node, the invalidate instruction for invalidating a memory range specified across a fabric interconnect.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: March 21, 2023
    Assignee: Intel Corporation
    Inventors: Karthik Kumar, Thomas Willhalm, Francesc Guim Bernat, Brian J. Slechta
  • Patent number: 11138101
    Abstract: Systems, apparatuses and methods may provide for detecting an issued request in a queue that is shared by a plurality of domains in a memory architecture, wherein the plurality of domains are associated with non-uniform access latencies. Additionally, a destination domain associated with the issued request may be determined. Moreover, a first set of additional requests may be prevented from being issued to the queue if the issued request satisfies an overrepresentation condition with respect to the destination domain and the first set of additional requests are associated with the destination domain. In one example, a second set of additional requests are permitted to be issued to the queue while the first set of additional requests are prevented from being issued to the queue, wherein the second set of additional requests are associated with one or more remaining domains in the plurality of domains.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: October 5, 2021
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Raj K. Ramanujan, Brian J. Slechta
  • Patent number: 10951516
    Abstract: Technologies for quality of service based throttling in a fabric architecture include a network node of a plurality of network nodes interconnected across the fabric architecture via an interconnect fabric. The network node includes a host fabric interface (HFI) configured to facilitate the transmission of data to/from the network node, monitor quality of service levels of resources of the network node used to process and transmit the data, and detect a throttling condition based on a result of the monitored quality of service levels. The HFI is further configured to generate and transmit a throttling message to one or more of the interconnected network nodes in response to having detected a throttling condition. The HFI is additionally configured to receive a throttling message from another of the network nodes and perform a throttling action on one or more of the resources based on the received throttling message. Other embodiments are described herein.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: March 16, 2021
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Raj K. Ramanujan, Brian J. Slechta
  • Publication number: 20210073138
    Abstract: Embodiments of the invention include a machine-readable medium having stored thereon at least one instruction, which if performed by a machine causes the machine to perform a method that includes decoding, with a node, an invalidate instruction; and executing, with the node, the invalidate instruction for invalidating a memory range specified across a fabric interconnect.
    Type: Application
    Filed: November 17, 2020
    Publication date: March 11, 2021
    Applicant: Intel Corporation
    Inventors: Karthik KUMAR, Thomas WILLHALM, Francesc GUIM BERNAT, Brian J. SLECHTA
  • Patent number: 10846230
    Abstract: Embodiments of the invention include a machine-readable medium having stored thereon at least one instruction, which if performed by a machine causes the machine to perform a method that includes decoding, with a node, an invalidate instruction; and executing, with the node, the invalidate instruction for invalidating a memory range specified across a fabric interconnect.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Karthik Kumar, Thomas Willhalm, Francesc Guim Bernat, Brian J. Slechta
  • Patent number: 10389839
    Abstract: An apparatus comprises a processor to generate, in anticipation of receipt of a read request for data of a data set, a prefetch request to retrieve the data set from a memory device, the prefetch request to comprise at least one parameter indicating a size of the data set. The processor is further to cause transmission of the prefetch request to the memory device and in response to a read request for at least a portion of the data set, request the at least a portion of the data set from a cache storing a copy of the data set, wherein the cache is to store the copy of the data set after the copy is received from the memory device in response to the prefetch request.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: August 20, 2019
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Raj K. Ramanujan, Brian J. Slechta
  • Publication number: 20190199620
    Abstract: Technologies for quality of service based throttling in a fabric architecture include a network node of a plurality of network nodes interconnected across the fabric architecture via an interconnect fabric. The network node includes a host fabric interface (HFI) configured to facilitate the transmission of data to/from the network node, monitor quality of service levels of resources of the network node used to process and transmit the data, and detect a throttling condition based on a result of the monitored quality of service levels. The HFI is further configured to generate and transmit a throttling message to one or more of the interconnected network nodes in response to having detected a throttling condition. The HFI is additionally configured to receive a throttling message from another of the network nodes and perform a throttling action on one or more of the resources based on the received throttling message. Other embodiments are described herein.
    Type: Application
    Filed: March 4, 2019
    Publication date: June 27, 2019
    Inventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Raj K. Ramanujan, Brian J. Slechta
  • Publication number: 20190171556
    Abstract: Systems, apparatuses and methods may provide for detecting an issued request in a queue that is shared by a plurality of domains in a memory architecture, wherein the plurality of domains are associated with non-uniform access latencies. Additionally, a destination domain associated with the issued request may be determined. Moreover, a first set of additional requests may be prevented from being issued to the queue if the issued request satisfies an overrepresentation condition with respect to the destination domain and the first set of additional requests are associated with the destination domain. In one example, a second set of additional requests are permitted to be issued to the queue while the first set of additional requests are prevented from being issued to the queue, wherein the second set of additional requests are associated with one or more remaining domains in the plurality of domains.
    Type: Application
    Filed: November 29, 2018
    Publication date: June 6, 2019
    Inventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Raj K. Ramanujan, Brian J. Slechta
  • Patent number: 10237169
    Abstract: Technologies for quality of service based throttling in a fabric architecture include a network node of a plurality of network nodes interconnected across the fabric architecture via an interconnect fabric. The network node includes a host fabric interface (HFI) configured to facilitate the transmission of data to/from the network node, monitor quality of service levels of resources of the network node used to process and transmit the data, and detect a throttling condition based on a result of the monitored quality of service levels. The HFI is further configured to generate and transmit a throttling message to one or more of the interconnected network nodes in response to having detected a throttling condition. The HFI is additionally configured to receive a throttling message from another of the network nodes and perform a throttling action on one or more of the resources based on the received throttling message. Other embodiments are described herein.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: March 19, 2019
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Raj K. Ramanujan, Brian J. Slechta
  • Patent number: 10146681
    Abstract: Systems, apparatuses and methods may provide for detecting an issued request in a queue that is shared by a plurality of domains in a memory architecture, wherein the plurality of domains are associated with non-uniform access latencies. Additionally, a destination domain associated with the issued request may be determined. Moreover, a first set of additional requests may be prevented from being issued to the queue if the issued request satisfies an overrepresentation condition with respect to the destination domain and the first set of additional requests are associated with the destination domain. In one example, a second set of additional requests are permitted to be issued to the queue while the first set of additional requests are prevented from being issued to the queue, wherein the second set of additional requests are associated with one or more remaining domains in the plurality of domains.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: December 4, 2018
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Raj K. Ramanujan, Brian J. Slechta
  • Publication number: 20180165215
    Abstract: Embodiments of the invention include a machine-readable medium having stored thereon at least one instruction, which if performed by a machine causes the machine to perform a method that includes decoding, with a node, an invalidate instruction; and executing, with the node, the invalidate instruction for invalidating a memory range specified across a fabric interconnect.
    Type: Application
    Filed: December 12, 2016
    Publication date: June 14, 2018
    Inventors: Karthik KUMAR, Thomas WILLHALM, Francesc GUIM BERNAT, Brian J. SLECHTA
  • Publication number: 20170353576
    Abstract: In one embodiment, an apparatus comprises a processor to generate, in anticipation of receipt of a read request for data of a data set, a prefetch request to retrieve the data set from a memory device, the prefetch request to comprise at least one parameter indicating a size of the data set. The processor is further to cause transmission of the prefetch request to the memory device and in response to a read request for at least a portion of the data set, request the at least a portion of the data set from a cache storing a copy of the data set, wherein the cache is to store the copy of the data set after the copy is received from the memory device in response to the prefetch request.
    Type: Application
    Filed: June 1, 2016
    Publication date: December 7, 2017
    Applicant: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Raj K. Ramanujan, Brian J. Slechta
  • Publication number: 20170289024
    Abstract: Technologies for quality of service based throttling in a fabric architecture include a network node of a plurality of network nodes interconnected across the fabric architecture via an interconnect fabric. The network node includes a host fabric interface (HFI) configured to facilitate the transmission of data to/from the network node, monitor quality of service levels of resources of the network node used to process and transmit the data, and detect a throttling condition based on a result of the monitored quality of service levels. The HFI is further configured to generate and transmit a throttling message to one or more of the interconnected network nodes in response to having detected a throttling condition. The HFI is additionally configured to receive a throttling message from another of the network nodes and perform a throttling action on one or more of the resources based on the received throttling message. Other embodiments are described herein.
    Type: Application
    Filed: April 1, 2016
    Publication date: October 5, 2017
    Inventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Raj K. Ramanujan, Brian J. Slechta
  • Publication number: 20170185351
    Abstract: Systems, apparatuses and methods may provide for detecting an issued request in a queue that is shared by a plurality of domains in a memory architecture, wherein the plurality of domains are associated with non-uniform access latencies. Additionally, a destination domain associated with the issued request may be determined. Moreover, a first set of additional requests may be prevented from being issued to the queue if the issued request satisfies an overrepresentation condition with respect to the destination domain and the first set of additional requests are associated with the destination domain. In one example, a second set of additional requests are permitted to be issued to the queue while the first set of additional requests are prevented from being issued to the queue, wherein the second set of additional requests are associated with one or more remaining domains in the plurality of domains.
    Type: Application
    Filed: December 24, 2015
    Publication date: June 29, 2017
    Inventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Raj K. Ramanujan, Brian J. Slechta