Patents by Inventor Brian J. Vincent

Brian J. Vincent has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9171645
    Abstract: Integrated circuits with memory built-in self-test (BIST) logic and methods of testing using the same are disclosed. The method includes setting an address window for locating defects in a memory array. The method further includes comparing output data of the memory array to expected data to determine that a defect exists at location “M” in the memory array within the address window. The method further includes storing, in registers, the address M and a resultant bit fail vector associated with the location “M” of the defect found in the memory array. The method further includes resetting the registers to a null value and resetting the address window with a new minimum and maximum address pair, to compare the output data of the memory array to the expected data within the reset address window which excludes address M.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: October 27, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: Geovanny Rodriguez, Brian J. Vincent, Timothy J. Vonreyn
  • Publication number: 20140359383
    Abstract: Integrated circuits with memory built-in self-test (BIST) logic and methods of testing using the same are disclosed. The method includes setting an address window for locating defects in a memory array. The method further includes comparing output data of the memory array to expected data to determine that a defect exists at location “M” in the memory array within the address window. The method further includes storing, in registers, the address M and a resultant bit fail vector associated with the location “M” of the defect found in the memory array. The method further includes resetting the registers to a null value and resetting the address window with a new minimum and maximum address pair, to compare the output data of the memory array to the expected data within the reset address window which excludes address M.
    Type: Application
    Filed: May 28, 2013
    Publication date: December 4, 2014
    Inventors: Geovanny Rodriguez, Brian J. Vincent, Timothy J. Vonreyn
  • Patent number: 5018144
    Abstract: In scan testing of logic parts, this invention provides an inexpensive transition fault test by changing the sequence of application of the A/C and B clocks. In each machine test cycle the B clock is triggered first, and the A/C clock is triggered second. The periodicity of the clocks is not changed for a particular cycle, because in one cycle the B-to-A/C clocking that naturally occurs provides a minimum test window TP for performance and transition fault testing. Thus, less sophisticated scan test equipment can now provide both transition fault and stuck fault testing, without an increase in complexity or expense.
    Type: Grant
    Filed: April 28, 1989
    Date of Patent: May 21, 1991
    Assignee: International Business Machines Corporation
    Inventors: James L. Corr, Brian J. Vincent