Patents by Inventor Brian James Burkett
Brian James Burkett has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11903329Abstract: A method of reducing junction resistance variation for junctions in quantum information processing devices fabricated using two-step deposition processes. In one aspect, a method includes providing a dielectric substrate, forming a first resist layer on the dielectric substrate, forming a second resist layer on the first resist layer, and forming a third resist layer on the second resist layer. The first resist layer includes a first opening extending through a thickness of the first resist layer, the second resist layer includes a second opening aligned over the first opening and extending through a thickness of the second resist layer, and the third resist layer includes a third opening aligned over the second opening and extending through a thickness of the third resist layer.Type: GrantFiled: June 9, 2022Date of Patent: February 13, 2024Assignee: Google LLCInventor: Brian James Burkett
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Publication number: 20240047277Abstract: A method includes: forming an opening in a mask layer; measuring a feature size associated with a dimension of the opening; based on the feature size, determining a fabrication parameter; and forming a second layer in the opening. Forming the second layer is based on the fabrication parameter. A fabrication system includes a lithography system; a measurement system; a physical vapor deposition system; an oxidation system; and a control system. The control system is configured to control a feed-forward fabrication process.Type: ApplicationFiled: August 8, 2022Publication date: February 8, 2024Inventor: Brian James Burkett
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Publication number: 20230225223Abstract: Methods, systems and apparatus for forming Josephson junctions with reduced stray inductance. In one aspect, a device includes a substrate; a first superconductor layer on the substrate; an insulator layer on the first superconductor layer; a second superconductor layer on the insulator layer, wherein the first superconductor layer, the insulator layer, and the second superconductor layer form a superconductor tunnel junction; and a third superconductor layer directly on a surface of the first superconductor layer and directly on a surface of the second superconductor layer to provide a first contact to the superconducting tunnel junction and a second contact to the superconductor tunnel junction, respectively.Type: ApplicationFiled: March 6, 2023Publication date: July 13, 2023Inventors: Brian James Burkett, Ofer Naaman, Anthony Edward Megrant, Theodore Charles White
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Patent number: 11662664Abstract: A method of fabricating a circuit element, such as a quantum computing circuit element, including obtaining a lithography mask write file that includes mask information characterizing one or more mask features, obtaining a uniformity function that is configured to modify the mask information to compensate for a non-uniform deposition process, applying the uniformity function to the lithography mask write to obtain a modified lithography mask write file, and performing lithography as directed by the modified lithography mask write file.Type: GrantFiled: July 1, 2022Date of Patent: May 30, 2023Assignee: Google LLCInventors: Brian James Burkett, Rami Barends
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Publication number: 20230119165Abstract: A method of fabricating a circuit element, such as a quantum computing circuit element, including obtaining a lithography mask write file that includes mask information characterizing one or more mask features, obtaining a uniformity function that is configured to modify the mask information to compensate for a non-uniform deposition process, applying the uniformity function to the lithography mask write to obtain a modified lithography mask write file, and performing lithography as directed by the modified lithography mask write file.Type: ApplicationFiled: July 1, 2022Publication date: April 20, 2023Inventors: Brian James Burkett, Rami Barends
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Publication number: 20230114700Abstract: A substrate, a first layer disposed on the substrate, and a second layer disposed on the first layer are provided. An opening is etched through the second layer to the first layer. A first portion of the first layer is etched through the opening using a first etchant, to expose a surface of the substrate through the opening. A feature is deposited on the surface of the substrate through the opening. A second portion of the first layer is etched using a gaseous etchant, to release the substrate from the second layer.Type: ApplicationFiled: October 7, 2022Publication date: April 13, 2023Inventors: Brian James Burkett, John Mark Kreikebaum
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Patent number: 11600763Abstract: Methods, systems and apparatus for forming Josephson junctions with reduced stray inductance. In one aspect, a device includes a substrate; a first superconductor layer on the substrate; an insulator layer on the first superconductor layer; a second superconductor layer on the insulator layer, wherein the first superconductor layer, the insulator layer, and the second superconductor layer form a superconductor tunnel junction; and a third superconductor layer directly on a surface of the first superconductor layer and directly on a surface of the second superconductor layer to provide a first contact to the superconducting tunnel junction and a second contact to the superconductor tunnel junction, respectively.Type: GrantFiled: July 25, 2019Date of Patent: March 7, 2023Assignee: Google LLCInventors: Brian James Burkett, Ofer Naaman, Anthony Edward Megrant, Theodore Charles White
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Patent number: 11588094Abstract: A method of reducing junction resistance variation for junctions in quantum information processing devices fabricated using two-step deposition processes. In one aspect, a method includes providing a dielectric substrate (208), forming a first resist layer (210) on the dielectric substrate, forming a second resist layer (212) on the first resist layer, and forming a third resist layer (214) on the second resist layer. The first resist layer includes a first opening (216) extending through a thickness of the first resist layer, the second resist layer includes a second opening (218) aligned over the first opening and extending through a thickness of the second resist layer, and the third resist layer includes a third opening (220) aligned over the second opening and extending through a thickness of the third resist layer.Type: GrantFiled: September 18, 2017Date of Patent: February 21, 2023Assignee: Google LLCInventor: Brian James Burkett
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Publication number: 20220328749Abstract: A method of reducing junction resistance variation for junctions in quantum information processing devices fabricated using two-step deposition processes. In one aspect, a method includes providing a dielectric substrate, forming a first resist layer on the dielectric substrate, forming a second resist layer on the first resist layer, and forming a third resist layer on the second resist layer. The first resist layer includes a first opening extending through a thickness of the first resist layer, the second resist layer includes a second opening aligned over the first opening and extending through a thickness of the second resist layer, and the third resist layer includes a third opening aligned over the second opening and extending through a thickness of the third resist layer.Type: ApplicationFiled: June 9, 2022Publication date: October 13, 2022Inventor: Brian James Burkett
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Patent number: 11378890Abstract: A method of fabricating a circuit element, such as a quantum computing circuit element, including obtaining a lithography mask write file that includes mask information characterizing one or more mask features, obtaining a uniformity function that is configured to modify the mask information to compensate for a non-uniform deposition process, applying the uniformity function to the lithography mask write to obtain a modified lithography mask write file, and performing lithography as directed by the modified lithography mask write file.Type: GrantFiled: March 22, 2021Date of Patent: July 5, 2022Assignee: Google LLCInventors: Brian James Burkett, Rami Barends
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Publication number: 20210336121Abstract: Methods, systems and apparatus for forming Josephson junctions with reduced stray inductance. In one aspect, a device includes a substrate; a first superconductor layer on the substrate; an insulator layer on the first superconductor layer; a second superconductor layer on the insulator layer, wherein the first superconductor layer, the insulator layer, and the second superconductor layer form a superconductor tunnel junction; and a third superconductor layer directly on a surface of the first superconductor layer and directly on a surface of the second superconductor layer to provide a first contact to the superconducting tunnel junction and a second contact to the superconductor tunnel junction, respectively.Type: ApplicationFiled: July 25, 2019Publication date: October 28, 2021Inventors: Brian James Burkett, Ofer Naaman, Anthony Edward Megrant, Theodore Charles White
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Publication number: 20210208509Abstract: A method of fabricating a circuit element, such as a quantum computing circuit element, including obtaining a lithography mask write file that includes mask information characterizing one or more mask features, obtaining a uniformity function that is configured to modify the mask information to compensate for a non-uniform deposition process, applying the uniformity function to the lithography mask write to obtain a modified lithography mask write file, and performing lithography as directed by the modified lithography mask write file.Type: ApplicationFiled: March 22, 2021Publication date: July 8, 2021Inventors: Brian James Burkett, Rami Barends
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Patent number: 10990017Abstract: A method of fabricating a circuit element, such as a quantum computing circuit element, including obtaining a lithography mask write file that includes mask information characterizing one or more mask features, obtaining a uniformity function that is configured to modify the mask information to compensate for a non-uniform deposition process, applying the uniformity function to the lithography mask write to obtain a modified lithography mask write file, and performing lithography as directed by the modified lithography mask write file.Type: GrantFiled: December 1, 2017Date of Patent: April 27, 2021Assignee: Google LLCInventors: Brian James Burkett, Rami Barends
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Publication number: 20200279990Abstract: A method of reducing junction resistance variation for junctions in quantum information processing devices fabricated using two-step deposition processes. In one aspect, a method includes providing a dielectric substrate (208), forming a first resist layer (210) on the dielectric substrate, forming a second resist layer (212) on the first resist layer, and forming a third resist layer (214) on the second resist layer. The first resist layer includes a first opening (216) extending through a thickness of the first resist layer, the second resist layer includes a second opening (218) aligned over the first opening and extending through a thickness of the second resist layer, and the third resist layer includes a third opening (220) aligned over the second opening and extending through a thickness of the third resist layer.Type: ApplicationFiled: September 18, 2017Publication date: September 3, 2020Inventor: Brian James Burkett
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Publication number: 20190204753Abstract: A method of fabricating a circuit element, such as a quantum computing circuit element, including obtaining a lithography mask write file that includes mask information characterizing one or more mask features, obtaining a uniformity function that is configured to modify the mask information to compensate for a non-uniform deposition process, applying the uniformity function to the lithography mask write to obtain a modified lithography mask write file, and performing lithography as directed by the modified lithography mask write file.Type: ApplicationFiled: December 1, 2017Publication date: July 4, 2019Inventors: Brian James Burkett, Rami Barends