Patents by Inventor Brian Ji

Brian Ji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6115310
    Abstract: A wordline activation delay monitor circuit is disclosed herein which includes a sample wordline located within a data-storing array of a memory, wherein the sample wordline is selected or activated by circuitry having substantially the same structure or location within the memory as circuitry which selects or activates wordlines of the data-storing array. A circuit is disclosed which determines a wordline activation delay for a first subarray group within the memory by activating a sample wordline which is located within a data-storing array of a second subarray group. Corresponding methods are also disclosed.
    Type: Grant
    Filed: January 5, 1999
    Date of Patent: September 5, 2000
    Assignee: International Business Machines Corporation
    Inventors: Dmitry G. Netis, L. Brian Ji, Toshiaki Kirihata
  • Patent number: 6081479
    Abstract: A semiconductor memory in accordance with the present invention includes a data path including a plurality of hierarchical stages, each stage including a bit data rate which is different from the other stages. At least two prefetch circuits are disposed between the stages. The at least two prefetch circuits include at least two latches for receiving data bits and storing the data bits until a next stage in the hierarchy is capable of receiving the data bits. The at least two prefetch circuits are coupled between stages such that an overall data rate per stage between stages are substantially equal. Control signals control the at least two latches such that prefetch circuits maintain the overall data rate between the stages.
    Type: Grant
    Filed: June 15, 1999
    Date of Patent: June 27, 2000
    Assignees: Infineon Technologies North America Corp., International Business Machines Corporation
    Inventors: Brian Ji, Toshiaki Kirihata, Gerhard Mueller, David Hanson
  • Patent number: 6038634
    Abstract: A system is disclosed herein for stabilizing the current dissipation, voltage drop, and heating effects related to accessing blocks within first and second storage units of a double memory unit. The system includes a row selection unit located between the first and second storage units, which accesses storage locations of the first and second storage units according to first and second selection signals conducted from the outer extremities of the double memory unit to selected row locations. The blocks at corresponding distances from the outer extremities are numbered differently such that the sum of lengths of signal travel of the first and second selection signals to the numbered blocks remains relatively constant regardless of the block number which is selected for access.
    Type: Grant
    Filed: February 2, 1998
    Date of Patent: March 14, 2000
    Assignee: International Business Machines Corporation
    Inventors: L. Brian Ji, Toshiaki Kirihata