Abstract: A semiconductor chip with uniform topology includes a memory cell having a stacked capacitor self-aligned with a bitline. Thick insulation on the bitline and on interconnect wiring on supports circuits of the chip serves to provide the uniform topology and to provide for the self-alignment of the capacitor and bitline. Bitlines and support circuit interconnect wiring are both formed from the same level of metal but they are patterned in separate masking steps. The stacked capacitors are separated from each other by less than the minimum dimension of the photolithographic system used for fabrication.

Abstract: A computer graphics and display system is provided, comprising (i) a graphics system for outputting a first plurality of digital color signals; (ii) a first digital-to-analog converter (DAC) for converting the first plurality of digital color signals into a second plurality of analog color signals, the second plurality being less in number than the first plurality; (iii) a first analog-to-digital converter (ADC) for reconverting the second plurality of analog color signals back to the first plurality of digital color signals; and (iv) an LCD display device for receiving the reconverted first plurality of digital color signals. The first and second DACs and the first and second ADCs are implemented within the same integrated circuit (IC) chip. The first plurality of digital color signals comprises red, blue and green even pixels and red, blue and green odd pixels. Each color for both even and odd pixels is encoded onto a single pair of the first DACs by interleaving same color pixels onto the single pair.

Abstract: Structures and methods are presented for forming a body-substrate connector for an SOI FET. The connector is formed substantially co-aligned with the gate conductor on a side of the device that does not interfere with source and drain. The body is thus held close to the substrate potential and the connector provides a path for majority carriers to quickly leave the body. By contacting the body of the SOI MOSFET device in a manner that does not perturb the charge imaged by the gate, parasitic bipolar effects are eliminated while maintaining the desirable attributes of SOI MOSFET devices, such as low substrate bias sensitivity and steep sub-threshold slope. By forming the connector substantially co-aligned with the gate conductor the connection uses little or no surface area.