Patents by Inventor Brian Joseph Greene

Brian Joseph Greene has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10384338
    Abstract: A robotic vehicle is provided with an extendable arm and a mandible structure. The mandible structure includes a pair of mandibles with toothed portions that cooperatively engage such that the mandibles may be opened and closed by applying a force to only one of the pair of mandibles. The mandible structure hangs freely from the extendable arm and is balanced so that the mandible structure naturally maintains a substantially vertical orientation. In the closed position, the mandible structure defines an interior cavity suitable for securely grasping a ring.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: August 20, 2019
    Assignee: CARDINAL GIBBONS HIGH SCHOOL
    Inventors: Sean Michael Greene, Benjamin Gerard Gravel, Aaron Joseph Ruff, Sean Michael McDonald, Brian Alexander Nelson, Austin Laboy Schick, Colin Daniel Russell
  • Patent number: 7939413
    Abstract: An example embodiments are structures and methods for forming an FET with embedded stressor S/D regions (e.g., SiGe), a doped layer below the embedded S/D region adjacent to the isolation regions, and a stressor liner over reduced spacers of the FET gate. An example method comprising the following. We provide a gate structure over a first region in a substrate. The gate structure is comprised of gate dielectric, a gate, and sidewall spacers. We provide isolation regions in the first region spaced from the gate structure; and a channel region in the substrate under the gate structure. We form S/D recesses in the first region in the substrate adjacent to the sidewall spacers. We form S/D stressor regions filling the S/D recesses.
    Type: Grant
    Filed: December 8, 2005
    Date of Patent: May 10, 2011
    Assignees: Samsung Electronics Co., Ltd., Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Yung Fu Chong, Zhijiong Luo, Joo Chan Kim, Brian Joseph Greene, Kern Rim
  • Patent number: 7928436
    Abstract: A semiconductor structure that includes a monocrystalline germanium-containing layer, preferably substantially pure germanium, a substrate, and a buried insulator layer separating the germanium-containing layer from the substrate. A porous layer, which may be porous silicon, is formed on a substrate and a germanium-containing layer is formed on the porous silicon layer. The porous layer may be converted to a layer of oxide, which provides the buried insulator layer. Alternatively, the germanium-containing layer may be transferred from the porous layer to an insulating layer on another substrate. After the transfer, the insulating layer is buried between the latter substrate and the germanium-containing layer.
    Type: Grant
    Filed: May 14, 2008
    Date of Patent: April 19, 2011
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Brian Joseph Greene, Jack Allan Mandelman
  • Patent number: 7812397
    Abstract: A MOSFET structure includes a planar semiconductor substrate, a gate dielectric and a gate. A UT SOI channel extends to a first depth below the top surface of the substrate and is self-aligned to and is laterally coextensive with the gate. Source-drain regions, extend to a second depth greater than the first depth below the top surface, and are self-aligned to the UT channel region. A BOX1 region extends across the entire structure, and vertically from the second depth to a third depth below the top surface. An upper portion of a BOX2 region under the UT channel region is self-aligned to and is laterally coextensive with the gate, and extends vertically from the first depth to a third depth below the top surface, and where the third depth is greater than the second depth.
    Type: Grant
    Filed: July 1, 2008
    Date of Patent: October 12, 2010
    Assignee: International Business Machines Corporation
    Inventors: Changguo Cheng, Dureseti Chidambarrao, Brian Joseph Greene, Jack A. Mandelman, Kern Rim
  • Patent number: 7767541
    Abstract: A semiconductor structure that includes a monocrystalline germanium-containing layer, preferably substantially pure germanium, a substrate, and a buried insulator layer separating the germanium-containing layer from the substrate. A porous layer, which may be porous silicon, is formed on a substrate and a germanium-containing layer is formed on the porous silicon layer. The porous layer may be converted to a layer of oxide, which provides the buried insulator layer. Alternatively, the germanium-containing layer may be transferred from the porous layer to an insulating layer on another substrate. After the transfer, the insulating layer is buried between the latter substrate and the germanium-containing layer.
    Type: Grant
    Filed: October 26, 2005
    Date of Patent: August 3, 2010
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Brian Joseph Greene, Jack Allan Mandelman
  • Patent number: 7542330
    Abstract: An SRAM having asymmetrical FET pass gates and a method of fabricating an SRAM having asymmetrical FET pass gates. The pass gates are asymmetrical with respect to current conduction from the drain to the source of the pass gate being different from current conduction from the source to the drain of the pass gate.
    Type: Grant
    Filed: June 15, 2007
    Date of Patent: June 2, 2009
    Assignee: International Business Machines Corporation
    Inventors: Brian Joseph Greene, Chun-Yung Sung, Clement Wann, Robert Chi-Foon Wong, Ying Zhang
  • Patent number: 7507631
    Abstract: A method of forming and a structure of an electronic device. The method including: forming a trench in a single-crystal semiconductor substrate; forming a dopant diffusion barrier layer on sidewalls and a bottom of the trench; and epitaxially growing a single-crystal semiconductor layer in the trench, the single-crystal semiconductor layer filling the trench, the dopant diffusion barrier layer a barrier to diffusion of semiconductor dopants. Also a power transistor formed by the same method.
    Type: Grant
    Filed: July 6, 2006
    Date of Patent: March 24, 2009
    Assignee: International Business Machines Corporation
    Inventors: Brian Joseph Greene, Judson Robert Holt
  • Publication number: 20080310212
    Abstract: An SRAM having asymmetrical FET pass gates and a method of fabricating an SRAM having asymmetrical FET pass gates. The pass gates are asymmetrical with respect to current conduction from the drain to the source of the pass gate being different from current conduction from the source to the drain of the pass gate.
    Type: Application
    Filed: June 15, 2007
    Publication date: December 18, 2008
    Inventors: Brian Joseph Greene, Chun-Yung Sung, Clement Wann, Robert Chi-Foon Wong, Ying Zhang
  • Publication number: 20080283918
    Abstract: A MOSFET structure includes a planar semiconductor substrate, a gate dielectric and a gate. A UT SOI channel extends to a first depth below the top surface of the substrate and is self-aligned to and is laterally coextensive with the gate. Source-drain regions, extend to a second depth greater than the first depth below the top surface, and are self-aligned to the UT channel region. A BOX1 region extends across the entire structure, and vertically from the second depth to a third depth below the top surface. An upper portion of a BOX2 region under the UT channel region is self-aligned to and is laterally coextensive with the gate, and extends vertically from the first depth to a third depth below the top surface, and where the third depth is greater than the second depth.
    Type: Application
    Filed: July 1, 2008
    Publication date: November 20, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Dureseti Chidambarrao, Brian Joseph Greene, Jack A. Mandelman, Kern Rim
  • Patent number: 7442618
    Abstract: Structures and methods for forming keyhole shaped regions for isolation and/or stressing the substrate are shown. In a first embodiment, we form an inverted keyhole shaped trench in the substrate in the first opening preferably using a two step etch. Next, we fill the inverted keyhole trench with a material that insulates and/or creates stress on the sidewalls of the inverted keyhole trench. In a second embodiment, we form a keyhole stressor region adjacent to the gate and isolation structures. The keyhole stressor region creates stress near the channel region of the FET to improve FET performance. The stressor region can be filled with an insulator or a semiconductor material.
    Type: Grant
    Filed: July 16, 2005
    Date of Patent: October 28, 2008
    Assignees: Chartered Semiconductor Manufacturing, Ltd
    Inventors: Yung Fu Chong, Brian Joseph Greene, Siddhartha Panda, Nivo Rovedo
  • Publication number: 20080211054
    Abstract: A semiconductor structure that includes a monocrystalline germanium-containing layer, preferably substantially pure germanium, a substrate, and a buried insulator layer separating the germanium-containing layer from the substrate. A porous layer, which may be porous silicon, is formed on a substrate and a germanium-containing layer is formed on the porous silicon layer. The porous layer may be converted to a layer of oxide, which provides the buried insulator layer. Alternatively, the germanium-containing layer may be transferred from the porous layer to an insulating layer on another substrate. After the transfer, the insulating layer is buried between the latter substrate and the germanium-containing layer.
    Type: Application
    Filed: May 14, 2008
    Publication date: September 4, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Brian Joseph Greene, Jack Allan Mandelman
  • Patent number: 7405131
    Abstract: The example embodiments disclose devices and methods to prevent silicide strapping of the Source/Drain to Body in semiconductor devices with S/D stressor. We provide isolation regions in the substrate and a gate structure over the substrate. We form recesses in the substrate adjacent to the gate structure with disposable spacers and adjacent to the isolation regions. We provide stressor regions filling the recesses. The stress region can have a pit adjacent the isolation regions. We form stressor spacers at least partially in the pit on the sidewalls of the stressor regions. We form silicide regions over the stressor regions. The spacer on the stressor regions sidewalls inhibit the formation of silicide at the stressor region edge during the silicide process, thus preventing silicide strapping of the Source/Drain to Body.
    Type: Grant
    Filed: July 16, 2005
    Date of Patent: July 29, 2008
    Assignees: Chartered Semiconductor Manufacturing, Ltd., International Business Machines Corporation (IBM)
    Inventors: Yung Fu Chong, Brian Joseph Greene
  • Publication number: 20080009109
    Abstract: A method of forming and a structure of an electronic device. The method including: forming a trench in a single-crystal semiconductor substrate; forming a dopant diffusion barrier layer on sidewalls and a bottom of the trench; and epitaxially growing a single-crystal semiconductor layer in the trench, the single-crystal semiconductor layer filling the trench, the dopant diffusion barrier layer a barrier to diffusion of semiconductor dopants. Also a power transistor formed by the same method.
    Type: Application
    Filed: July 6, 2006
    Publication date: January 10, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian Joseph Greene, Judson Robert Holt
  • Patent number: 7132322
    Abstract: Form a dielectric layer on a semiconductor substrate. Deposit an amorphous Si film or a poly-Si film on the dielectric layer. Then deposit a SiGe amorphous-Ge or polysilicon-Ge thin film theteover. Pattern and etch the SiGe film using a selective etch leaving the SiGe thin film intact in a PFET region and removing the SiGe film exposing the top surface of the Si film in an NFET region. Anneal to drive Ge into the Si film in the PFET region. Deposit a gate electrode layer covering the SiGe film in the PFET region and cover the exposed portion of the Si film in the NFET region. Pattern and etch the gate electrode layer to form gates. Form FET devices with sidewall spacers and source regions and drains regions in the substrate aligned with the gates.
    Type: Grant
    Filed: May 11, 2005
    Date of Patent: November 7, 2006
    Assignee: International Business Machines Corporation
    Inventors: Brian Joseph Greene, Kern Rim, Clement Wann