Patents by Inventor Brian Joseph Sassone

Brian Joseph Sassone has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multi-bus data processing system in which all data words in high level cache memories have any one of four states and all data words in low level cache memories have any one of three states
    Patent number: 6223260
    Abstract: A data processing system is comprised of: a system bus having a main memory coupled thereto; multiple high level cache memories, each of which has a first port coupled to said system bus and a second port coupled to a respective processor bus; and each processor bus being coupled through respective low level cache memories to respective digital computers. In the high level cache memories, data words are stored with respective tag bits which identify each data word as being stored in one of only four states which are shared, modified, invalid, or exclusive. In the low level cache memories, data words are stored with respective tag bits which identify each data word as being stored in only one of three states which are shared, modified or invalid.
    Type: Grant
    Filed: September 10, 1997
    Date of Patent: April 24, 2001
    Assignee: Unisys Corporation
    Inventors: Manoj Gujral, Brian Joseph Sassone, Laurence Paul Flora, David Edgar Castle