Abstract: A process for generating a logic netlist suitable for a logic simulator model from a data or netlist representation (11) of a circuit of transistors and resistors in either emitter coupled logic or current mode logic technology. The logic netlist is formed to serve as a logic simulation model having logic elements structured and patterned to follow the circuit representation at the transistor level, most commonly known as a netlist, which includes the resistors and the overall circuit interconnection. The logic extraction process (1.0, 2.0) identifies active and passive circuit elements connected according to prescribed criteria to eliminate elements which do not contribute to logic functionality as well as identifying elements essential to providing the logic functionality. A systematic approach keeps track of circuit nodes to enable the appropriate interconnection of logic elements patterned after the physical circuit represented as the netlist.