Abstract: A switched power circuit to control a common-mode signal. The switched power circuit includes a first switch and a second switch configured to generate switch mode voltage between a first node and a second node. The switched power circuit further includes a feedback circuit that is configured to detect common-mode voltage generated between the first node and the second node by a first signal generated by the first switch and a second signal generated by the second switch, and incrementally adjust a timing parameter of the first signal to adjust the common-mode signal.

Abstract: A circuit to control a switching characteristic of a switching device. The circuit includes a driver circuit comprising an output port, where the driver circuit is configured to generate, at the output port, a control signal to actuate the switching device within a first time period. The control signal comprising at least one electrical pulse, where a pulse width of the at least one electrical pulse being shorter than the first time period. The circuit also includes a coupling circuit that is configured to use the control signal to actuate the switching device to establish a target switching characteristic of the switching device according to a modulation of the at least one electrical pulse. The control circuit is also configured to provide a greater impedance to the control signal than an impedance of the output terminal of the driver circuit.

Abstract: An electronic circuit comprises a power switch and a fault detection circuit. The power switch circuit includes a power switch transistor. The fault detection circuit includes a comparator circuit configured to monitor a voltage across the power switch transistor and compare the voltage to a varying threshold voltage that decreases with time, and produce an indication of a circuit fault when the voltage of the power switch transistor is greater than the time varying threshold voltage.

Abstract: An electronic circuit comprises a power switch circuit and a fault detection circuit. The power switch circuit includes a transistor. The fault detection circuit includes a first comparator circuit configured to compare a monitored voltage of the transistor to a detection threshold voltage and produce an indication of a circuit fault according to the comparing, and a delay circuit configured to delay the comparing by the first comparator circuit according to slew rate of the monitored voltage.

Abstract: An electronic circuit comprises a power switch and a fault detection circuit. The power switch circuit includes a power switch transistor. The fault detection circuit includes a comparator circuit configured to monitor a voltage across the power switch transistor and compare the voltage to a varying threshold voltage that decreases with time, and produce an indication of a circuit fault when the voltage of the power switch transistor is greater than the time varying threshold voltage.

Abstract: An electronic circuit comprises a power switch circuit and a fault detection circuit. The power switch circuit includes a transistor. The fault detection circuit includes a first comparator circuit configured to compare a monitored voltage of the transistor to a detection threshold voltage and produce an indication of a circuit fault according to the comparing, and a delay circuit configured to delay the comparing by the first comparator circuit according to slew rate of the monitored voltage.

Abstract: A circuit to control a switching characteristic of a switching device. The circuit includes a driver circuit comprising an output port, where the driver circuit is configured to generate, at the output port, a control signal to actuate the switching device within a first time period. The control signal comprising at least one electrical pulse, where a pulse width of the at least one electrical pulse being shorter than the first time period. The circuit also includes a coupling circuit that is configured to use the control signal to actuate the switching device to establish a target switching characteristic of the switching device according to a modulation of the at least one electrical pulse. The control circuit is also configured to provide a greater impedance to the control signal than an impedance of the output terminal of the driver circuit.

Abstract: A switched power circuit to control a common-mode signal. The switched power circuit includes a first switch and a second switch configured to generate switch mode voltage between a first node and a second node. The switched power circuit further includes a feedback circuit that is configured to detect common-mode voltage generated between the first node and the second node by a first signal generated by the first switch and a second signal generated by the second switch, and incrementally adjust a timing parameter of the first signal to adjust the common-mode signal.

Abstract: A device is configured to control a transition timing of a switching DC/DC converter for providing power to a load device. The load device has a first operational phase that is sensitive to external noise and a second operational phase that is immune to the external noise. The device includes an input terminal coupled to an external device to receive a start signal of the first operational phase for the load device. The device also includes control circuitry configured to, responsive to the start signal, control a transition frequency of the DC/DC converter to avoid transitioning an output of the switching DC/DC converter during the first operational phase.

Abstract: This disclosure describes a circuit implementation providing the functions necessary to implement an isolated I2C bidirectional port. The technique implements a current source as a pull up device on at least one side of the isolation system. The circuit manages and communicates bidirectional data across an isolation barrier. A method of communicating bidirectional signals and an I2C acknowledge (ACK) or clock stretching through an isolation channel is disclosed.

Abstract: This disclosure describes a circuit implementation providing the functions necessary to implement an isolated I2C bidirectional port. The technique implements a current source as a pull up device on at least one side of the isolation system. The circuit manages and communicates bidirectional data across an isolation barrier. A method of communicating bidirectional signals and an I2C acknowledge (ACK) or clock stretching through an isolation channel is disclosed.