Abstract: The invention comprises a system bus apparatus and method for a multi-arm, multiprocessor computer system having a main memory and localized buffer cache memories at each processor. Each block of data in a cache includes tag bits which identifies the condition of the data block in relation to the corresponding data in main memory and other caches. The system bus (SYSBUS) comprises three subparts; 1) a MESSAGE/DATA bus, 2) a REQUEST/GRANT bus and 3) a BCU bus. The MESSAGE/DATA bus is coupled to every device on the system and is used for transferring messages, data and addresses. The REQUEST/GRANT bus couples between every device on an arm of the system and that arm's bus control unit (BCU). The BCU bus couples between the various BCUs.

Abstract: A method and apparatus for accessing a selected entry in a first memory by means of an index formed by combining an index and a stored backpointer of a second memory's entry corresponding to the selected entry in the first memory.

Abstract: A look ahead fetch system for a pipelined digital computer is provided for predicting in advance of decoding the outcome of a branch instruction. The system includes a branch cache having a plurality of associative sets for storing branch target addresses indexed by the lowest significant bits of the corresponding branch instruction's address. A memory for storing a coupling bit vector indicative for each branch cache set of whether the set contains a corresponding branch target address. The coupling bit vector is used to guide prediction logic to the correct branch cache sets for qualifying the entry there contained having an index corresponding to a fetched instruction's address for formulating a prediction of the next instruction to be processed.

Abstract: A branch cache system for use with a pipelined processor having overlapping parcel prefetch and execution stages. The system includes a plurality of memory sets for storing a plurality of indexed sets of predicted branch addresses, and control circuitry which determines whether there is stored in one of the memory sets a predicted branch address which corresponds to a branch instruction fetched by the prefetch stage. The execution stage is commanded, responsive to detection of a predicted branch address corresponding to that branch instruction, to execute the branch instruction to the predicted branch address. Alternatively, the system includes one or more memory sets for storing predicted branch addresses and corresponding alignment values which represent whether the boundary of a prefetched branch instruction, which is prefetched as one or more parcels, aligns with the fixed boundary of the one or more parcels containing that instruction.

Abstract: A Hashing Indexer For a Branch Cache for use in a pipelined digital processor that employs macro-instructions utilizing interpretation by micro-instructions. Each of the macro-instructions has an associated address and each of the micro instructions has an associated address. The hashing indexer includes a look-ahead-fetch system including a branch cache memory coupled to the prefetch section. An indexed table of branch target addressess each of which correspond to the address of a previously fetched instruction is stored in the branch cache memory. A predetermined number of bits representing the address of the macro-instruction being fetched is hashed with a predetermined number of bits representing the address of the micro-instruction being invoked. The indexer is used to apply the hashing result as an address to the branch memory in order to read out a unique predicted branch target address that is predictive of a branch for the hashed macro-instruction bits and micro-instruction bits.