Patents by Inventor Brian Keith Kirkpatrick

Brian Keith Kirkpatrick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device including SiON gate dielectric with portions having different nitrogen concentrations
    Patent number: 8748996
    Abstract: An integrated circuit (IC) includes a substrate having a top semiconductor surface including at least one MOS device including a source and a drain region spaced apart to define a channel region. A SiON gate dielectric layer that has a plurality of different N concentration portions is formed on the top semiconductor surface. A gate electrode is on the SiON layer. The plurality of different N concentration portions include (i) a bottom portion extending to the semiconductor interface having an average N concentration of <2 atomic %, (ii) a bulk portion having an average N concentration >10 atomic %, and (iii) a top portion on the bulk portion extending to a gate electrode interface having an average N concentration that is ?2 atomic % less than a peak N concentration of the bulk portion.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: June 10, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: James Joseph Chambers, Hiroaki Niimi, Brian Keith Kirkpatrick
  • SEMICONDUCTOR DEVICE INCLUDING SION GATE DIELECTRIC WITH PORTIONS HAVING DIFFERENT NITROGEN CONCENTRATIONS
    Publication number: 20130228879
    Abstract: An integrated circuit (IC) includes a substrate having a top semiconductor surface including at least one MOS device including a source and a drain region spaced apart to define a channel region. A SiON gate dielectric layer that has a plurality of different N concentration portions is formed on the top semiconductor surface. A gate electrode is on the SiON layer. The plurality of different N concentration portions include (i) a bottom portion extending to the semiconductor interface having an average N concentration of <2 atomic %, (ii) a bulk portion having an average N concentration >10 atomic %, and (iii) a top portion on the bulk portion extending to a gate electrode interface having an average N concentration that is ?2 atomic % less than a peak N concentration of the bulk portion.
    Type: Application
    Filed: April 15, 2013
    Publication date: September 5, 2013
    Applicant: Texas Instruments Incorporated
    Inventors: James Joseph CHAMBERS, Hiroaki NIIMI, Brian Keith KIRKPATRICK
  • Semiconductor device including SiON gate dielectric with portions having different nitrogen concentrations
    Patent number: 8441078
    Abstract: An integrated circuit (IC) includes a substrate having a top semiconductor surface including at least one MOS device including a source and a drain region spaced apart to define a channel region. A SiON gate dielectric layer that has a plurality of different N concentration portions is formed on the top semiconductor surface. A gate electrode is on the SiON layer. The plurality of different N concentration portions include (i) a bottom portion extending to the semiconductor interface having an average N concentration of <2 atomic %, (ii) a bulk portion having an average N concentration >10 atomic %, and (iii) a top portion on the bulk portion extending to a gate electrode interface having an average N concentration that is ?2 atomic % less than a peak N concentration of the bulk portion.
    Type: Grant
    Filed: February 23, 2010
    Date of Patent: May 14, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: James Joseph Chambers, Hiroaki Niimi, Brian Keith Kirkpatrick
  • SEMICONDUCTOR DEVICE INCLUDING SION GATE DIELECTRIC WITH PORTIONS HAVING DIFFERENT NITROGEN CONCENTRATIONS
    Publication number: 20110204454
    Abstract: An integrated circuit (IC) includes a substrate having a top semiconductor surface including at least one MOS device including a source and a drain region spaced apart to define a channel region. A SiON gate dielectric layer that has a plurality of different N concentration portions is formed on the top semiconductor surface. A gate electrode is on the SiON layer. The plurality of different N concentration portions include (i) a bottom portion extending to the semiconductor interface having an average N concentration of <2 atomic %, (ii) a bulk portion having an average N concentration >10 atomic %, and (iii) a top portion on the bulk portion extending to a gate electrode interface having an average N concentration that is ?2 atomic % less than a peak N concentration of the bulk portion.
    Type: Application
    Filed: February 23, 2010
    Publication date: August 25, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: James Joseph Chambers, Hiroaki Niimi, Brian Keith Kirkpatrick