Patents by Inventor Brian Keith Langendorf

Brian Keith Langendorf has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8234458
    Abstract: A method and system for maintaining cache coherency across a serial interface bus such as a Peripheral Component Interconnect Express (PCIe) bus. The method includes generating a snoop request (SNP) to determine whether first data stored in a local memory is coherent relative to second data stored in a data cache, the snoop request including destination information that identifies the data cache on the serial interface bus, and causing the snoop request to be transmitted over the serial interface bus to a second processor. The method further includes extracting a cache line address from the snoop request, determining whether the second data is coherent, generating a complete message (CPL) indicating that the first data is coherent with the second data, and causing the complete message to be transmitted over the bus to the first processor. The snoop request and complete messages may be vendor defined messages.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: July 31, 2012
    Assignee: NVIDIA Corporation
    Inventors: Brian Keith Langendorf, David B. Glasco, Michael Brian Cox, Jonah M. Alben
  • Patent number: 7969445
    Abstract: A system, method, and computer program product are provided for broadcasting write operations in a multiple-target system. In use, a write operation is received at one of a plurality of apertures of an address space. Such write operation is then replicated to produce a plurality of write operations. To this end, the write operations may be broadcasted to a plurality of targets. At least one of the targets includes another one of the apertures that produces at least one additional write operation.
    Type: Grant
    Filed: June 20, 2007
    Date of Patent: June 28, 2011
    Assignee: NVIDIA Corporation
    Inventors: Brian Keith Langendorf, James P. Reilley, Suyash Ranjan
  • Patent number: 7920701
    Abstract: A digital content system is disclosed. A security engine disposed in a bridge provides cryptographic services. Clear text digital data received from a central processing unit is encrypted and transferred via the bridge over unsecured data paths as cipher text.
    Type: Grant
    Filed: December 14, 2005
    Date of Patent: April 5, 2011
    Assignee: Nvidia Corporation
    Inventors: Michael Brian Cox, Henry Packard Moreton, Brian Keith Langendorf, David G. Reed
  • Publication number: 20100146218
    Abstract: A method for executing processing operations using data stored in a memory. The method includes generating a snoop request configured to determine whether first data stored in a local memory is coherent relative to second data stored in a data cache, the snoop request including destination information that identifies the data cache on a bus, and a cache line address identifying where in the data cache the second data is located. The method further includes causing the snoop request to be transmitted over the bus to the second processor, extracting the cache line address from the snoop request, determining whether the second data is coherent, generating a complete message that includes completion information indicating that the first data is coherent with the second data, and causing the complete message to be transmitted over the bus to the first processor.
    Type: Application
    Filed: December 9, 2008
    Publication date: June 10, 2010
    Inventors: Brian Keith Langendorf, David B. Glasco, Michael Brian Cox, Jonah M. Alben
  • Patent number: 7650645
    Abstract: Circuits, methods, and apparatus that provide for trusted transactions between a device and system memory. In one exemplary embodiment of the present invention, a host processor asserts and de-asserts trust over a virtual wire. The device accesses certain data if the host processor provides a trusted instruction for it to do so. Once the device attempts to access this certain data, or perform a certain type of data access, a memory controller allows the access on the condition that the host processor previously made the trusted instruction. The device then accepts data if trust is asserted during the data transfer.
    Type: Grant
    Filed: May 20, 2005
    Date of Patent: January 19, 2010
    Assignee: NVIDIA Corporation
    Inventors: Brian Keith Langendorf, Michael Brian Cox
  • Publication number: 20080316842
    Abstract: A system, method, and computer program product are provided for broadcasting write operations in a multiple-target system. In use, a write operation is received at one of a plurality of apertures of an address space. Such write operation is then replicated to produce a plurality of write operations. To this end, the write operations may be broadcasted to a plurality of targets. At least one of the targets includes another one of the apertures that produces at least one additional write operation.
    Type: Application
    Filed: June 20, 2007
    Publication date: December 25, 2008
    Inventors: Brian Keith Langendorf, James P. Reilley, Suyash Ranjan
  • Patent number: 7461211
    Abstract: A system, apparatus, and method are disclosed for storing and prioritizing predictions to anticipate nonsequential accesses to a memory. In one embodiment, an exemplary apparatus is configured as a prefetcher for predicting accesses to a memory. The prefetcher includes a prediction generator configured to generate a prediction that is unpatternable to an address. Also, the prefetcher also can include a target cache coupled to the prediction generator to maintain the prediction in a manner that determines a priority for the prediction. In another embodiment, the prefetcher can also include a priority adjuster. The priority adjuster sets a priority for a prediction relative to other predictions. In some cases, the placement of the prediction is indicative of the priority relative to priorities for the other predictions. In yet another embodiment, the prediction generator uses the priority to determine that the prediction is to be generated before other predictions.
    Type: Grant
    Filed: August 17, 2004
    Date of Patent: December 2, 2008
    Assignee: Nvidia Corporation
    Inventors: Ziyad S. Hakura, Brian Keith Langendorf, Stefano A. Pescador, Radoslav Danilak, Brad W. Simeral
  • Patent number: 7441087
    Abstract: A system, apparatus, and method are disclosed for managing predictive accesses to memory. In one embodiment, an exemplary apparatus is configured as a prediction inventory that stores predictions in a number of queues. Each queue is configured to maintain predictions until a subset of the predictions is either issued to access a memory or filtered out as redundant. In another embodiment, an exemplary prefetcher predicts accesses to a memory. The prefetcher comprises a speculator for generating a number of predictions and a prediction inventory, which includes queues each configured to maintain a group of items. The group of items typically includes a triggering address that corresponds to the group. Each item of the group is of one type of prediction. Also, the prefetcher includes an inventory filter configured to compare the number of predictions against one of the queues having the either the same or different prediction type as the number of predictions.
    Type: Grant
    Filed: August 17, 2004
    Date of Patent: October 21, 2008
    Assignee: NVIDIA Corporation
    Inventors: Ziyad S. Hakura, Brian Keith Langendorf, Stefano A. Pescador, Radoslay Danilak, Brad W. Simeral
  • Patent number: 7260686
    Abstract: A system, apparatus, and method are disclosed for storing predictions as well as examining and using one or more caches for anticipating accesses to a memory. In one embodiment, an exemplary apparatus is a prefetcher for managing predictive accesses with a memory. The prefetcher can include a speculator to generate a range of predictions, and multiple caches. For example, the prefetcher can include a first cache and a second cache to store predictions. An entry of the first cache is addressable by a first representation of an address from the range of predictions, whereas an entry of the second cache is addressable by a second representation of the address. The first and the second representations are compared in parallel against the stored predictions of either the first cache and the second cache, or both.
    Type: Grant
    Filed: August 17, 2004
    Date of Patent: August 21, 2007
    Assignee: Nvidia Corporation
    Inventors: Ziyad S. Hakura, Radoslav Danilak, Brad W. Simeral, Brian Keith Langendorf, Stefano A. Pescador, Dmitry Vyshetsky
  • Patent number: 7206902
    Abstract: A system, apparatus, and method are disclosed for predicting accesses to memory. In one embodiment, an exemplary apparatus comprises a processor configured to execute program instructions and process program data, a memory including the program instructions and the program data, and a memory processor. The memory processor can include a speculator configured to receive an address containing the program instructions or the program data. Such a speculator can comprise a sequential predictor for generating a configurable number of sequential addresses. The speculator can also include a nonsequential predictor configured to associate a subset of addresses to the address and to predict a group of addresses based on at least one address of the subset, wherein at least one address of the subset is unpatternable to the address.
    Type: Grant
    Filed: August 17, 2004
    Date of Patent: April 17, 2007
    Assignee: NVIDIA Corporation
    Inventors: Ziyad S. Hakura, Brian Keith Langendorf, Stefano A. Pescador, Radoslav Danilak, Brad W. Simeral
  • Patent number: 7053901
    Abstract: Embodiments of the invention accelerate at least one special purpose processor, such as a GPU, or a driver managing a special purpose processor, by using at least one co-processor. Advantageously, embodiments of the invention are fault-tolerant in that the at least one GPU or other special purpose processor is able to execute all computations, although perhaps at a lower level of performance, if the at least one co-processor is rendered inoperable. The co-processor may also be used selectively, based on performance considerations.
    Type: Grant
    Filed: December 11, 2003
    Date of Patent: May 30, 2006
    Assignee: NVIDIA Corporation
    Inventors: Jen-Hsun Huang, Michael Brian Cox, Ziyad S. Hakura, John S. Montrym, Brad W. Simeral, Brian Keith Langendorf, Blanton Scott Kephart, Franck R. Diard