Abstract: A method and apparatus for enabling the correct architectural sequencing of fetched instructions prior to allowing the instructions to complete in the processor pipeline to reduce the occurrence of pipeline breaks. A branch processing unit (BPU) is designed to perform sequence checks for the addresses of all instructions fetched into the pipeline (i.e., both in-line and branch instructions) by the instruction fetch unit (IFU). A first instruction is fetched. The address of the next instruction in the architectural sequence is computed and stored within the BPU. The next instruction is fetched and its address is compared to the next instruction address stored in BPU to determine if it is the correct address. If the next instruction address matches that of the architectural sequence, the instruction is permitted to “live” (i.e., continue through to completion). When the address does not match, the instruction is killed (i.e., not allowed to complete) and a new instruction is fetched by the IFU.

Abstract: A pipelined processor and method are disclosed for speculatively determining dependencies. The processor processes a plurality of instructions in order. A speculative detection circuit which takes multiple clock cycles to operate determines whether a dependency exists. The speculative detection circuit inserts a single-cycle pipeline stall only in response to a determination that a speculative dependency exists.

Abstract: An instruction fetching system (and/or architecture) which may be utilized by a high-frequency short-pipeline microprocessor, for efficient fetching of both in-line and target instructions. The system contains an instruction fetching unit (IFU), having a control logic and associated components for controlling a specially designed instruction cache (I-cache). The I-cache is a sum-address cache, i.e., it receives two address inputs, which compiled by a decoder to provide the address of the line of instructions desired fetch. The I-cache is designed with an array of cache lines that can contain 32 instructions, and three buffers that each have a capacity of 32 instructions.

Abstract: A pipelined processor and method are disclosed including an improved history file unit. The pipelined processor processes a plurality of instructions in order. A register file is included which includes a different read port coupled to each register field in an instruction buffer for reading data from the register file. A history file unit is included and is coupled to each of the read ports of the register file for receiving a copy of all data read from the register file.