Abstract: A gravity irrigation system includes a distribution piping having apertures to distribute water to a field, and a valve located upstream of the distribution piping. The valve limits a pressure of the water being delivered to the distribution piping. The system also includes a sump to receive the water at a lowest elevation of the field, a depth sensor disposed within the sump, and a return pump disposed at least partially within the sump to move the water to an elevated portion of the field. The system also includes a motor to drive the return pump, and a power source coupled to a variable frequency drive that powers the motor and controls a motor speed proportionately to an indication of the depth sensor. The system also includes a transfer piping to bring the water from the return pump to a check valve and to the distribution piping.

Abstract: A circuit and method for using hardware to calculate a first derivative of the number of performance events that occur in a microprocessor during a predetermined period of time. This first derivative indicates a frequency of such performance events, which can be used as either a predictor of future problems or needs, or may be used to invoke a corrective action.

Abstract: A data receiver circuit in a receiving chip provides the capability to characterize an interface, which includes one or more inter-chip communication lines, between a transmitting chip and the receiving chip by transmitting the data across a primary data path and a secondary data path, latching the data in the secondary data path using a clock signal that is skewed relative to a clock signal used to latch the primary data path, comparing the data latched from the primary and secondary data paths, and recording errors. Because the primary data path is not impacted by the test cycle, the test cycle may be run while data associated with applications running on the system are transmitted across the inter-chip communication lines.

Abstract: Methods for creating and synthesizing multiple instances of a component from a single logical model are provided. In general, a flag is provided which designates a design methodology for use in instantiating the component. Depending on the value of the flag, a block of hardware design code defining an instance of the component according to a design methodology is loaded.