Patents by Inventor Brian Kopec

Brian Kopec has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230146395
    Abstract: The present disclosure provides compounds that are inhibitors of PIKfyve and/or PI3 kinases, and are therefore useful for the treatment of neurological diseases treatable by inhibition of PIKfyve and/or PI3 kinases. Also provided are pharmaceutical compositions containing such compounds, and methods of treatment of neurological diseases using such compounds.
    Type: Application
    Filed: March 8, 2021
    Publication date: May 11, 2023
    Applicant: Verge Analytics, Inc.
    Inventors: Mark D. Rosen, Robert A. Galemmo, Jr., Weiling Liang, Irene Y. Choi, Brian Kopec, Jane Rhodes
  • Publication number: 20230133203
    Abstract: The present disclosure provides compounds that are inhibitors of PIKfyve kinases useful for the treatment of neurological diseases treatable by inhibition of PIKfyve. Also provided are pharmaceutical compositions containing such compounds, and methods of treatment using such compounds.
    Type: Application
    Filed: January 12, 2021
    Publication date: May 4, 2023
    Applicant: Verge Analytics, Inc.
    Inventors: Mark D. Rosen, Robert A. Galemmo, JR., Weiling Liang, Brian Kopec, Irene Y. Choi, Jane Rhodes
  • Publication number: 20070174584
    Abstract: A processor having a multistage pipeline includes a TLB and a TLB controller. In response to a TLB miss signal, the TLB controller initiates a TLB reload, requesting address translation information from either a memory or a higher-level TLB, and placing that information into the TLB. The processor flushes the instruction having the missing virtual address, and refetches the instruction, resulting in re-insertion of the instruction at an initial stage of the pipeline above the TLB access point. The initiation of the TLB reload, and the flush/refetch of the instruction, are performed substantially in parallel, and without immediately stalling the pipeline. The refetched instruction is held at a point in the pipeline above the TLB access point until the TLB reload is complete, so that the refetched instruction generates a “hit” in the TLB upon its next access.
    Type: Application
    Filed: January 20, 2006
    Publication date: July 26, 2007
    Inventors: Brian Kopec, Victor Augsburg, James Dieffenderfer, Jeffrey Bridges, Thomas Sartorius
  • Publication number: 20070005933
    Abstract: A processor includes a memory configured to store data in a plurality of pages, a TLB, and a TLB controller. The TLB is configured to search, when accessed by an instruction having a virtual address, for address translation information that allows the virtual address to be translated into a physical address of one of the plurality of pages, and to provide the address translation information if the address translation information is found within the TLB. The TLB controller is configured to determine whether a current instruction and a subsequent instruction seek access to a same page within the plurality of pages, and if so, to prevent TLB access by the subsequent instruction, and to utilize the results of the TLB access of a previous instruction for the current instruction.
    Type: Application
    Filed: June 29, 2005
    Publication date: January 4, 2007
    Inventors: Brian Kopec, Victor Augsburg, James Dieffenderfer, Jeffrey Bridges, Thomas Sartorius