Abstract: Control logic in a memory device initiates a program operation to program one or more memory cells of a first sub-block of a memory array, the program operation including a seeding phase. During the seeding phase, a first wordline voltage is caused to be applied to a first wordline segment associated with a first portion of the memory array. During the seeding phase, a second wordline voltage is caused to be applied to a second wordline segment associated with a second portion of the memory array, where the first wordline voltage and the second wordline voltage cause a seeding bias voltage to be applied to the first sub-block group and inhibit application of the seeding bias voltage to the second sub-block group.

Abstract: A memory device includes a memory array comprising memory cells and control logic operatively coupled with the memory array. The control logic causes, as part of a true erase sub-operation, an erase pulse to be applied to one or more sub-blocks of the memory array. The control logic tracks a number of suspend commands received from a processing device, including suspend commands received while memory cells of the one or more sub-blocks are being erased. The control logic causes, in response to receiving each suspend command, the true erase sub-operation to be suspended to enable performing a non-erase memory operation. The control logic, in response to the number of suspend commands satisfying a threshold criterion, alerts the processing device to terminate sending suspend commands.

Abstract: A memory device includes a memory array of memory cells and control logic operatively coupled with the memory array. The control logic is to perform operations including: initiating a true erase sub-operation by causing an erase pulse to be applied to one or more sub-blocks of the memory array; tracking, a number of suspend commands received from a processing device during time periods that a memory line of the memory array is caused to ramp towards an erase voltage of the erase pulse; causing, in response to receiving each suspend command, the true erase sub-operation to be suspended to enable performing a non-erase memory operation; and in response to the number of suspend commands satisfying a threshold criterion, alerting the processing device to terminate sending suspend commands until after completion of the true erase sub-operation.

Abstract: A memory device includes a memory array of memory cells and control logic operatively coupled with the memory array. The control logic is to perform operations including: initiating a true erase sub-operation by causing an erase pulse to be applied to one or more sub-blocks of the memory array; tracking, a number of suspend commands received from a processing device during time periods that a memory line of the memory array is caused to ramp towards an erase voltage of the erase pulse; causing, in response to receiving each suspend command, the true erase sub-operation to be suspended to enable performing a non-erase memory operation; and in response to the number of suspend commands satisfying a threshold criterion, alerting the processing device to terminate sending suspend commands until after completion of the true erase sub-operation.

Abstract: A system for performing near infrared spectroscopy (NIRS) monitors tissue oxygenation and/or hemodynamics. The system comprises a sensor coupled to a controller and/or processing device. The sensor comprises a light source which is operable to emit light of various distinct wavelengths and a detector which is operable to collect corresponding backscattered light.

Abstract: A spinal facet fusion device is provided. The device includes a working sleeve having a first surface with a first port and a second port extending there through. The first port has a first perimeter and the second port having a second perimeter, wherein the first port is larger than the second port. A guide wire sleeve having a body with a proximal end and a distal end and a first outer perimeter is provided. The first outer perimeter is sized and shaped to be slidingly disposed within the second port, the guide wire sleeve having a channel extending longitudinally from the proximal end through the distal end, the body further having a stop feature on the distal end. An implementing device having a second outer perimeter is sized to be slidingly received within the first perimeter.

Abstract: A spinal facet fusion device is provided. The device includes a working sleeve having a first surface with a first port and a second port extending there through. The first port has a first perimeter and the second port having a second perimeter, wherein the first port is larger than the second port. A guide wire sleeve having a body with a proximal end and a distal end and a first outer perimeter is provided. The first outer perimeter is sized and shaped to be slidingly disposed within the second port, the guide wire sleeve having a channel extending longitudinally from the proximal end through the distal end, the body further having a stop feature on the distal end. An implementing device having a second outer perimeter is sized to be slidingly received within the first perimeter.