Abstract: Enclosure (16) for housing a coupler (18) between a driving rod (20) and a driven rod (22) comprises a first and a second preferably cylindrical pieces (30, 28). Said pieces are sized so that the first piece (30) is able to slide telescopically within the second piece (28) and are threaded to engage each other when in operation the enclosure (16) is in a close position, thereby the enclosure (16) being able to retain lubricant in the inside. For service, after having drained the lubricant from the enclosure (16), the two pieces are loosened by screwing the first piece (30) until the end of the thread is reached, and then the first piece (30) is slideably telescoped into the second piece (28), thereby setting the enclosure (16) in an open position an enabling easy access to the rod coupler (18).

Abstract: A current-sharing multiphase sliding-mode switching power supply (24) and method of operation are presented. A bipolar power source (22) is coupled to a switch (30) for each phase (28), each switch (30) is in turn coupled to an inductance (32), and a capacitance (36) is coupled to the inductances (32) and across a load (26). A sliding-surface generator (78) generates a sliding surface (?). A current-balance control (80) computes a reference current as a summary statistic (IX) of inductive currents (IL) through the inductances (32), calculates an error current (IE) for each phase (28) as a difference between the summary statistic (IX) and the inductive current (IL), and adjusts the sliding surface (?) for each phase (28) so that all inductive currents (IL) are substantially equal to the summary statistic (IX). A switching circuit (138) switches the switches (30) in response to the sliding surface (?).

Abstract: A data driven clock recovery system comprising a viterbi detector for detecting data and tentatively deciding the closest approximation, and a circuit for retrieving the tentative decision in stages. Preferably, the clock recovery system further comprises a combination series-parallel comparison circuit for selecting one value of a set of values for input to the viterbi and for applying said one value to the viterbi.

Abstract: A non-recursive filter for receiving samples and generating a filtered signal, the filter comprises a plurality of successive partial summation units, each partial summation unit having multiplier for multiplying an undelayed state of each of the samples, and an adder for adding multiplied samples; and a plurality of delay elements each coupled to the adder for receiving added samples and for providing a delayed output of the added samples to a successive partial summation unit.

Abstract: A data driven clock recovery system comprising a viterbi for detecting data and tentatively deciding the closest approximation, and a circuit for retrieving the tentative decision in stages. Preferably, the clock recovery system further comprises a combination series-parallel comparison circuit for selecting one value of a set of values for input to the viterbi and for applying said one value to the viterbi.

Abstract: A compensation system for calibrating an amplifier having a compensation input including a sigma delta converter, a counter, a memory, adjust logic, a DAC, a pair of compensation capacitors, and a pair of current to voltage (I/V) converters. The converter converts an offset voltage to a bit stream. The counter stores a sum value indicative of the output offset. The memory stores a digital bias value. The adjust logic determines an adjust value based on the sum value and adjusts the stored digital bias value based on the adjust value. The DAC converts the digital bias value to a differential bias current. The compensation capacitors apply a compensation voltage to a compensation input of the amplifier. The I/V converters charge the compensation capacitors using the differential bias current. The adjust logic may use upper and lower thresholds and adjust the digital bias value by one LSB for each compensation cycle.

Abstract: A calibration system and method for a resistor ladder that employs relative measurement and adjustment between pairs of resistors. The system includes a resistor tree of complementary pairs of programmable resistors coupled to the resistor ladder, a measurement circuit that measures voltage differences between complementary pairs of programmable resistors, and control logic. The control logic controls the measurement circuit to measure a voltage difference between each complementary pair of programmable resistors and adjusts the relative resistance of each complementary pair of programmable resistors to equalize voltage. The measurement is facilitated by a sigma-delta ADC that converts a measured voltage difference into a bit stream. The programmable resistors are implemented with binary weighted resistors that are digitally adjusted one LSB at a time. Lower and upper adjustment thresholds may be employed to avoid unnecessary over-adjustments while maintaining a requisite level of accuracy.

Abstract: A calibration system and method for a resistor ladder that employs relative measurement and adjustment between pairs of resistors. The system includes a resistor tree of complementary pairs of programmable resistors coupled to the resistor ladder, a measurement circuit that measures voltage differences between complementary pairs of programmable resistors, and control logic. The control logic controls the measurement circuit to measure a voltage difference between each complementary pair of programmable resistors and adjusts the relative resistance of each complementary pair of programmable resistors to equalize voltage. The measurement is facilitated by a sigma-delta ADC that converts a measured voltage difference into a bit stream. The programmable resistors are implemented with binary weighted resistors that are digitally adjusted one LSB at a time. Lower and upper adjustment thresholds may be employed to avoid unnecessary over-adjustments while maintaining a requisite level of accuracy.

Abstract: A compensation system for calibrating an amplifier having a compensation input including a sigma delta converter, a counter, a memory, adjust logic, a DAC, a pair of compensation capacitors, and a pair of current to voltage (I/V) converters. The converter converts an offset voltage to a bit stream. The counter stores a sum value indicative of the output offset. The memory stores a digital bias value. The adjust logic determines an adjust value based on the sum value and adjusts the stored digital bias value based on the adjust value. The DAC converts the digital bias value to a differential bias current. The compensation capacitors apply a compensation voltage to a compensation input of the amplifier. The I/V converters charge the compensation capacitors using the differential bias current. The adjust logic may use upper and lower thresholds and adjust the digital bias value by one LSB for each compensation cycle.

Abstract: A multistage ADC that subranges and interpolates, and that amplifies selected subranges to convert an analog signal to a stream of digital values. The ADC samples the analog signal and provides a stream of sample signals. A first stage flash converts each sample signal into a first multiple bit value and subranges a reference ladder according to the first multiple bit value into selected reference signals. Each additional secondary stage amplifies a selected subrange of signals from a prior stage, flash converts the amplified residual signals to provide an additional multiple bit value, interpolates each set of amplified residual signals and subranges the interpolated signals according to the corresponding multiple bit value. A final stage amplifies and flash converts to determine a final multiple bit value. An error corrector combines each set of multiple bit values into a digital value.