Abstract: A source synchronous test methodology and apparatus. In one embodiment, an integrated circuit (IC) configured for source synchronous I/O transactions may be a device under test (DUT) and may be mounted to a load board for testing. The load board may be electrically coupled to a test system. The test system may shift first test data into a first IC on the load board. The first chip may then transmit the first test data through a source synchronous line, or a source synchronous link having a plurality of lines, to a second IC. Second test data produced responsive to the source synchronous transmission is then shifted from the second IC to the tester. The second test data is then analyzed. The analysis may comprise comparing the second data to expected data, and/or may also comprise analyzing the second data with respect to an eye window.

Abstract: A method and apparatus for automated calibration of I/O over a multi-variable eye window is provided. A transmitter may conduct data transmissions to a receiver of an integrated circuit (IC) over a plurality of signal lines. The data transmissions may be conducted according to a certain parameters or sets of parameters. Parameters may include voltage levels at which signals are transmitted or timing delays. The receiver may determine whether the correct data value was received over each signal line. The results may be recorded in a storage mechanism in the same IC as the receiver. The storage mechanism may, for each signal line, store a pass/fail result corresponding to the particular parameters for the data transmission. The system may select the parameters which subsequent transmissions are to be conducted over each of the plurality of signal lines from the storage mechanism.

Abstract: A method and mechanism for arbitrating and transmitting data. A first transaction and a second transaction are detected. The first transaction is targeted to a first domain and the second transaction is targeted to a second domain different than the first domain. Subsequent to receiving the transactions, arbitration domains corresponding to each are determined. In response to detecting the arbitration domains are not equal, the first and second transaction may be transmitted concurrently. However, if the arbitration domains are determined to be equal, arbitration is performed and transmission of the first and second transactions is serialized. Also contemplated is generating masks corresponding to each of the received transactions. The masks which are generated include an indication of the target domain of the corresponding transaction. When the transaction is conveyed to a port for transmittal, its mask is conveyed as well.

Abstract: An apparatus or method for testing the setup time and hold time specifications of a chip. An apparatus according to the invention would include a first chip, a second chip, and multiple links coupling the first chip to the second chip. One of the links carries a clock signal between the chips. Other links carrying data have propagation delays different from the propagation delay of the link carrying the clock signal. The relation of the delays for the data links to the delay for the clock link determines a particular setup and/or hold time tested.

Abstract: A system and method for testing signal interconnections using built-in self test (BIST). BIST functionality is designed into the various chips of a computer system. These chips include a transmit unit, a receive unit, a control logic unit, and a central logic unit. A control logic unit associated with a signal block (i.e. a group of signals) configures the signal block for either testing or normal operation. The central logic unit performs test pattern generation for all signal blocks on a given chip. Chips may act as either a master or slave chip during testing. When acting as a master chip, the transmit unit of the chip drives test patterns onto one or more signal lines. The receive unit of the slave chip returns a corresponding test pattern to the master chip after receiving the transmitted test pattern. A receive unit on the master chip receives the corresponding test patterns and performs verification. All tests occur at the operational clock speed of the computer system.

Abstract: A self cleaning bearing assembly for use in a dehydrator washer for particulate solids which comprises a feed reservoir for water and particulate solids and an inclined main screw conveyor having a projecting shaft lower end portion submerged in the reservoir. The bearing assembly comprises a housing having an end cap at one end and an opening at the opposite end in communication with the interior of the feed reservoir. The housing has its longitudinal center line coincident with the main screw conveyor and a stub shaft mounted on the end cap of the bearing assembly also has its axis coincident with that of the main crew conveyor and its shaft. The projecting lower end portion of the main conveyor shaft and the stub shaft are disposed with the stub shaft in radially spaced relationship within the main shaft and a sleeve bearing is disposed in the radial space between the stub shaft and the main shaft.

Abstract: A method and mechanism for configuring a node in a computing system to route data to a predetermined observation point. A node in a computing device or system is configured to identify and convey an observation data stream via a non-critical path. A non-critical path is configured within the computer system for the transmission of the generated stream of data to a convenient client location where the data may be observed. This stream of data is routed through the computer system via disabled, replicated, monitor or other links which correspond to a non-critical path. The observation data stream conveyed by the node may be generated by the node and correspond to an internal state of the node. Additionally, the node may be configured to duplicate and convey received data streams or extract debug data from a received data stream for conveyance to a predetermined observation point.

Abstract: In a computer system having a first repeater and a second repeater, the first repeater coupled to the second repeater by a bus, the first repeater operable to transmit a transaction and a control signal to the second repeater, a method, performed by the second repeater, of generating an error comprising: predicting, in a first cycle, that a transaction should be transmitted from the first repeater to the second repeater; determining if a control signal was received within a predetermined number of cycles of the first cycle; and if the control signal is not received within the predetermined number of cycles of the first cycle, then generating an error.

Abstract: A method of synchronizing arbiters. The method is performed by a computer system that has a first repeater, a second repeater that is coupled to the first repeater, and a third repeater that is coupled to the first repeater. The method includes: instructing the second repeater to cease issuing transactions to the first repeater; synchronizing an arbiter within the second repeater with an arbiter within the third repeater; instructing the second repeater to begin issuing transactions to the first repeater; and instructing the third repeater to begin issuing transactions to the first repeater.

Abstract: A computer system including a first repeater; a second repeater coupled to the first repeater; and a third repeater coupled to the first repeater. The second repeater is also coupled to a first client and a second client. The second repeater contains a distributed arbiter that predicts whether the first repeater will send a transaction to the second repeater.

Abstract: A computer system including a first repeater and a second repeater that is coupled to the first repeater. The computer system also includes a third repeater that is coupled to the first repeater. The first repeater contains a first arbiter that arbitrates transactions between the first repeater and the second repeater and also arbitrates transactions between the first repeater and the third repeater. The second repeater receives transactions from the first repeater and contains a second arbiter that predicts receipt of transactions from the first repeater to the second repeater.

Abstract: A computer system that includes a first repeater and a second repeater. The second repeater is coupled to the first repeater. The second repeater contains circuitry that causes the second repeater to cease issuing transactions to the first repeater for at least one bus cycle if the second repeater has issued “P,” a positive integer, consecutive transactions to the first repeater. The computer system also includes a third repeater that is coupled to the first repeater. The first repeater also includes an arbiter that gives priority to transactions being sent from the first repeater to the third repeater over transactions being sent from the third repeater to the first repeater.

Abstract: A self cleaning bearing assembly for use in a dehydrator washer for particulate solids which comprises a feed reservoir for water and particulate solids and an inclined main screw conveyor having a projecting shaft lower end portion submerged in the reservoir. The bearing assembly comprises a housing having an end cap at one end and an opening at the opposite end in communication with the interior of the feed reservoir. The housing has its longitudinal center line coincident with the main screw conveyor and a stub shaft mounted on the end cap of the bearing assembly also has its axis coincident with that of the main crew conveyor and its shaft. The projecting lower end portion of the main conveyor shaft and the stub shaft are disposed with the stub shaft in radially spaced relationship within the main shaft and a sleeve bearing is disposed in the radial space between the stub shaft and the main shaft.

Abstract: A concrete structure formed using an extender that connects to a web member at least partially disposed within a side panel. The extender may be used to extend the length of a connector that interconnects opposed side panels, used to provide additional surface area to which concrete can bond if, for example, forming a tilt-up wall, or used as a strapping location with a flexible linking member. It is noted that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to ascertain quickly the subject matter of the technical disclosure. The abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims pursuant to 37 C.F.R. § 1.72(b).

Abstract: Hyperlinear chromosomes are arrays of parameters stored in a computer readable memory, for use in implementing a genetic algorithm. Each chromosome may represent the mapping of a problem, including physical parameters, onto constituent genes which are addressed in memory as multiple, intersecting vectors in n-dimensions, where n is >2. A computing system is adapted to perform hyperlinear crossover, reproduction and fitness evaluation on the hyperlinear chromosomes. An adaptive computing system produces optimized control signals based on the attainment of a desired level of fitness of one or more hyperlinear chromosomes.