Abstract: An arrangement of semiconductor devices to monitor semiconductor defects. There is a first semiconductor device arranged in proximity to a second semiconductor device, the second semiconductor device having a plurality of temperature sensing devices at locations in the second semiconductor device; a plurality of through silicon vias extending between the first semiconductor device and the second semiconductor device to electrically connect the first semiconductor device to the second semiconductor device; and a testing program to cause the plurality of temperature sensing devices in the second semiconductor device to sense the temperature at a plurality of corresponding locations in the first semiconductor device such that a predetermined rise in temperature at one location of the plurality of temperature sensing devices in the second semiconductor device is indicative of a defect in the corresponding location in the first semiconductor device. Methods of monitoring defects are also disclosed.

Abstract: An arrangement of semiconductor devices to monitor semiconductor defects. There is a first semiconductor device arranged in proximity to a second semiconductor device, the second semiconductor device having a plurality of temperature sensing devices at locations in the second semiconductor device; a plurality of through silicon vias extending between the first semiconductor device and the second semiconductor device to electrically connect the first semiconductor device to the second semiconductor device; and a testing program to cause the plurality of temperature sensing devices in the second semiconductor device to sense the temperature at a plurality of corresponding locations in the first semiconductor device such that a predetermined rise in temperature at one location of the plurality of temperature sensing devices in the second semiconductor device is indicative of a defect in the corresponding location in the first semiconductor device. Methods of monitoring defects are also disclosed.

Abstract: A DRAM array in an SOI wafer having a uniform BOX layer extending throughout the array eliminates the collar oxide step in processing; connects the buried plates with an implant that, in turn, is connected to a conductive plug extending through the device layer and the box that is biased at ground; while the pass transistors are planar NFETs having floating bodies that have a leakage discharge path to ground through a grounded bitline.

Abstract: A DRAM array in an SOI wafer having a uniform BOX layer extending throughout the array eliminates the collar oxide step in processing; connects the buried plates with an implant that, in turn, is connected to a conductive plug extending through the device layer and the box that is biased at ground; while the pass transistors are planar NFETs having floating bodies that have a leakage discharge path to ground through a grounded bitline.