Abstract: A voltage level translator circuit for translating an input signal referenced to a first voltage supply to an output signal referenced to a second voltage supply includes an input stage for receiving the input signal and a latch circuit for storing a signal at an output of the latch circuit which is representative of a logical state of the input signal. The latch circuit includes an input coupled to the input stage. The voltage level translator circuit further includes a feedback circuit coupled between the input and the output of the latch circuit. The feedback circuit is operative to maintain a desired logic state of the voltage level translator circuit when the second voltage supply powers up before the first voltage supply. In this manner, the voltage level translator circuit is configured to provide an output signal having a predictable logic state over a wide variation of PVT conditions and/or voltage supply ramp rates.

Abstract: A buffer design for an integrated circuit that has adjustable slew rate control, yet requires significantly less space to fabricate than does a conventional buffer with slew rate control. A new slew rate control circuit design is added to a Complementary Metal Oxide Semiconductor CMOS buffer to implement slew rate control in the buffer (e.g., selection between a high slew rate and a low slew rate). The new slew rate control circuit requires significantly less space to fabricate, and when applied to each buffer in an given integrated circuit, e.g., input/output buffers that may be placed along the periphery of the integrated circuit, the savings can be extraordinary.