Patents by Inventor Brian Le
Brian Le has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230166122Abstract: A multi-function therapeutic system comprising a housing having a top portion having a first radiation therapy unit mounted therein for generating and applying light energy to a person, a bottom portion including a hydrogen therapy unit for supplying hydrogen to the person, and an intermediate bed portion disposed between the top portion and bottom portion. The intermediate bed portion includes an electromagnetic therapy unit for generating and applying electromagnetic energy to the person. The system can also include a vibration therapy unit associated with one or more of the bottom portion and the intermediate bed portion for generating and applying vibrational energy to the person, and a control unit for controlling the first radiation therapy unit, the hydrogen therapy unit, the electromagnetic therapy unit, and the sound therapy unit.Type: ApplicationFiled: June 17, 2022Publication date: June 1, 2023Inventors: Brian Le GETTE, Steven YOUNG
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Publication number: 20220347135Abstract: Spontaneous preterm birth (sPTB) is premature delivery prior to 37 weeks of pregnancy and is a leading cause of infant mortality worldwide. sPTB is associated with a unique gene expression profile. Identified herein are numerous safe and proven therapeutic compositions used for unrelated indications that have the biological effect of reversing, in part, the gene expression profile of sPTB and which can be used in preventative or interventional treatments to prevent, delay, or ameliorate sPTB. The repurposed drugs include several Class A and Class B therapeutics that are regarded as safe or low risk in pregnant subjects.Type: ApplicationFiled: March 20, 2020Publication date: November 3, 2022Applicants: The Regents of the University of California, The Leland Stanford Junior UniversityInventors: Marina Sirota, Brian Le, Ronald Wong, David Stevenson
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Patent number: 11026793Abstract: Systems and methods for magnetic induction of a penile prosthesis are disclosed. The magnetic induction system includes a wand that has a coil arrangement covered with a thermal and electrical insulator sheath operable to generate an alternating magnetic field. The coil arrangement of the sheath is configured to receive the length of the penile prosthesis therein. The penile prosthesis may be made from a shape memory material such that application of alternating magnetic fields generated by the magnetic induction system induces eddy currents that raise the temperature of the penile prosthesis to a temperature above the austenitic transformation temperature that allows the penile prosthesis to achieve an erect state.Type: GrantFiled: December 21, 2018Date of Patent: June 8, 2021Assignee: The Board of Trustees of Southern Illinois UniversityInventors: Alberto Colombo, Kevin McVary, Brian Le
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Publication number: 20200258572Abstract: A monolithic three-dimensional memory array is provided that includes a plurality of global bit lines disposed above a substrate, a plurality of vertically-oriented bit lines disposed above the global bit lines, a plurality of word lines disposed above the global bit lines, a plurality of memory cells coupled between the vertically-oriented bit lines and the word lines, and a plurality of isolation elements coupled between the vertically-oriented bit lines and the global bit lines. Each isolation element includes a vertical thin-film transistor and a threshold selector device.Type: ApplicationFiled: February 12, 2019Publication date: August 13, 2020Applicant: SANDISK TECHNOLOGIES LLCInventors: Abhijit Bandyopadhyay, Christopher J. Petti, Brian Le
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Patent number: 10734073Abstract: A monolithic three-dimensional memory array is provided that includes a plurality of global bit lines disposed above a substrate, a plurality of vertically-oriented bit lines disposed above the global bit lines, a plurality of word lines disposed above the global bit lines, a plurality of memory cells coupled between the vertically-oriented bit lines and the word lines, and a plurality of isolation elements coupled between the vertically-oriented bit lines and the global bit lines. Each isolation element includes a vertical thin-film transistor and a threshold selector device.Type: GrantFiled: February 12, 2019Date of Patent: August 4, 2020Assignee: SanDisk Technologies LLCInventors: Abhijit Bandyopadhyay, Christopher J. Petti, Brian Le
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Patent number: 10714534Abstract: A method is provided that includes forming a memory cell that includes a memory element coupled in series with an isolation element. The isolation element includes a vertical thin-film transistor and a threshold selector device.Type: GrantFiled: February 12, 2019Date of Patent: July 14, 2020Assignee: SanDisk Technologies LLCInventors: Abhijit Bandyopadhyay, Christopher J. Petti, Brian Le
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Publication number: 20190391718Abstract: A method, a system, and an article are provided for managing a scrolling operation on a computer display. An example method can include: providing a plurality of cells for presenting graphical elements on a user device; advancing a sequence of the cells through a visible area on a display of the user device; moving a first cell that is no longer within the visible area to one of a plurality of cell recycle pools; moving a second cell from one of the plurality of cell recycle pools to a cell generation area; generating a graphical element for the second cell within the cell generation area; and advancing the second cell from the cell generation area into the visible area on the display of the user device.Type: ApplicationFiled: June 18, 2019Publication date: December 26, 2019Inventors: Bingjie Cao, Brian Le, Shutong Yu
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Patent number: 10374013Abstract: A method is provided that includes forming a bit line above a substrate; forming a word line above the substrate, and forming a non-volatile memory cell between the bit line and the word line. The non-volatile memory cell includes a non-volatile memory material coupled in series with an isolation element. The isolation element includes a first electrode, a second electrode, and a semiconductor layer and a barrier layer disposed between the first electrode and the second electrode.Type: GrantFiled: March 30, 2017Date of Patent: August 6, 2019Assignee: SanDisk Technologies LLCInventors: Abhijit Bandyopadhyay, Christopher J. Petti, Natalie Nguyen, Brian Le
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Publication number: 20190133767Abstract: Systems and methods for magnetic induction of a penile prosthesis are disclosed. The magnetic induction system includes a wand that has a coil arrangement covered with a thermal and electrical insulator sheath operable to generate an alternating magnetic field. The coil arrangement of the sheath is configured to receive the length of the penile prosthesis therein. The penile prosthesis may be made from a shape memory material such that application of alternating magnetic fields generated by the magnetic induction system induces eddy currents that raise the temperature of the penile prosthesis to a temperature above the austenitic transformation temperature that allows the penile prosthesis to achieve an erect state.Type: ApplicationFiled: December 21, 2018Publication date: May 9, 2019Inventors: Alberto Colombo, Kevin McVary, Brian Le
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Patent number: 10195034Abstract: Systems and methods for magnetic induction of a penile prosthesis are disclosed. The magnetic induction system includes a wand that has a coil arrangement covered with a thermal and electrical insulator sheath operable to generate an alternating magnetic field. The coil arrangement of the sheath is configured to receive the length of the penile prosthesis therein. The penile prosthesis may be made from a shape memory material such that application of alternating magnetic fields generated by the magnetic induction system induces eddy currents that raise the temperature of the penile prosthesis to a temperature above the austenitic transformation temperature that allows the penile prosthesis to achieve an erect state.Type: GrantFiled: November 21, 2016Date of Patent: February 5, 2019Assignee: Board of Trustees of Southern Illinois UniversityInventors: Alberto Colombo, Kevin McVary, Brian Le
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Publication number: 20180286918Abstract: A method is provided that includes forming a bit line above a substrate; forming a word line above the substrate, and forming a non-volatile memory cell between the bit line and the word line. The non-volatile memory cell includes a non-volatile memory material coupled in series with an isolation element. The isolation element includes a first electrode, a second electrode, and a semiconductor layer and a barrier layer disposed between the first electrode and the second electrode.Type: ApplicationFiled: March 30, 2017Publication date: October 4, 2018Applicant: SANDISK TECHNOLOGIES LLCInventors: Abhijit Bandyopadhyay, Christopher J. Petti, Natalie Nguyen, Brian Le
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Patent number: 9986878Abstract: A toilet seat hinge for mounting a toilet seat to a toilet bowl includes a hinge post and a pin extending through the hinge post and defining an axis. The pin is configured to attach the toilet seat to the hinge post for pivotal movement about the axis. The toilet seat hinge also includes a quick release mechanism for releasably securing the hinge post to the toilet bowl. The quick release mechanism includes a member coupled to the pin for pivotal movement about the axis. The member is pivotable about the axis between a first position in which the hinge post is secured to the toilet bowl, and a second position in which the hinge post is released from the toilet bowl.Type: GrantFiled: September 17, 2012Date of Patent: June 5, 2018Assignee: Bemis Manufacturing CompanyInventors: Michael Stelter, Brian Le Mahieu, John Seaman
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Publication number: 20170143491Abstract: Systems and methods for magnetic induction of a penile prosthesis are disclosed. The magnetic induction system includes a wand that has a coil arrangement covered with a thermal and electrical insulator sheath operable to generate an alternating magnetic field. The coil arrangement of the sheath is configured to receive the length of the penile prosthesis therein. The penile prosthesis may be made from a shape memory material such that application of alternating magnetic fields generated by the magnetic induction system induces eddy currents that raise the temperature of the penile prosthesis to a temperature above the austenitic transformation temperature that allows the penile prosthesis to achieve an erect state.Type: ApplicationFiled: November 21, 2016Publication date: May 25, 2017Inventors: Alberto Colombo, Kevin McVary, Brian Le
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Patent number: 9470358Abstract: Holders for electronic devices and systems, methods, and methods of making thereof. Electronic device holders include a base and a support rotatably coupled to the base. The support includes a base, a coupler, and a stand and is rotatable to a plurality of different or same orientations. The stand is rotatable outwardly and inwardly from and two fully retracted and fully extended positions and positions therebetween. In one or more extended positions, the stand can be supported by a support surface or a support device or apparatus.Type: GrantFiled: May 3, 2013Date of Patent: October 18, 2016Assignee: ZERO CHROMA LLCInventors: Brian Le Gette, David Reeb
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Patent number: 9368207Abstract: Operating ReRAM memory is disclosed herein. The memory cells may be trained prior to initially programming them. The training may help to establish a percolation path. In some aspects, a transistor limits current of the memory cell when training and programming. A higher current limit is used during training, which conditions the memory cell for better programming. The non-memory may be operated in unipolar mode. The memory cells can store multiple bits per memory cell. A memory cell can be SET directly from its present state to one at least two data states away. A memory cell can be RESET directly to the state having the next highest resistance. Program conditions, such as pulse width and/or magnitude, may depend on the state to which the memory cell is being SET. A higher energy can be used for programming higher current states.Type: GrantFiled: January 7, 2015Date of Patent: June 14, 2016Assignee: SanDisk Technologies Inc.Inventors: Abhijit Bandyopadhyay, Roy E Scheuerlein, Chandrasekhar R Gorla, Brian Le
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Publication number: 20150170742Abstract: Operating ReRAM memory is disclosed herein. The memory cells may be trained prior to initially programming them. The training may help to establish a percolation path. In some aspects, a transistor limits current of the memory cell when training and programming. A higher current limit is used during training, which conditions the memory cell for better programming. The non-memory may be operated in unipolar mode. The memory cells can store multiple bits per memory cell. A memory cell can be SET directly from its present state to one at least two data states away. A memory cell can be RESET directly to the state having the next highest resistance. Program conditions, such as pulse width and/or magnitude, may depend on the state to which the memory cell is being SET. A higher energy can be used for programming higher current states.Type: ApplicationFiled: January 7, 2015Publication date: June 18, 2015Applicant: SANDISK 3D LLCInventors: Abhijit Bandyopadhyay, Roy E. Scheuerlein, Chandrasekhar R. Gorla, Brian Le
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Patent number: 8995169Abstract: Operating ReRAM memory is disclosed herein. The memory cells may be trained prior to initially programming them. The training may help to establish a percolation path. In some aspects, a transistor limits current of the memory cell when training and programming. A higher current limit is used during training, which conditions the memory cell for better programming. The non-memory may be operated in unipolar mode. The memory cells can store multiple bits per memory cell. A memory cell can be SET directly from its present state to one at least two data states away. A memory cell can be RESET directly to the state having the next highest resistance. Program conditions, such as pulse width and/or magnitude, may depend on the state to which the memory cell is being SET. A higher energy can be used for programming higher current states.Type: GrantFiled: September 12, 2013Date of Patent: March 31, 2015Assignee: SanDisk 3D LLCInventors: Abhijit Bandyopadhyay, Roy E. Scheuerlein, Chandrasekhar R. Gorla, Brian Le
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Publication number: 20150070965Abstract: Non-volatile storage devices having reversible resistance storage elements are disclosed herein. In one aspect, a memory cell unit includes one or more memory cells and a transistor (e.g., FET) that is used to control (e.g., limit) current of the memory cells. The drain of the transistor may be connected to a first end of the memory cell. If the memory cell unit has multiple memory cells then the drain may be connected to a node that is common to a first end of each of the memory cells. The source of the transistor is connected to a common source line. The gate of the transistor may be connected to a word line. The same word line may connect to the transistor gate of several (or many) different memory cell units. A second end of the memory cell is connected to a bit line.Type: ApplicationFiled: September 12, 2013Publication date: March 12, 2015Applicant: SanDisk 3D LLCInventors: Abhijit Bandyopadhyay, Roy E. Scheuerlein, Chandrasekhar R. Gorla, Brian Le
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Publication number: 20150070966Abstract: Operating ReRAM memory is disclosed herein. The memory cells may be trained prior to initially programming them. The training may help to establish a percolation path. In some aspects, a transistor limits current of the memory cell when training and programming. A higher current limit is used during training, which conditions the memory cell for better programming. The non-memory may be operated in unipolar mode. The memory cells can store multiple bits per memory cell. A memory cell can be SET directly from its present state to one at least two data states away. A memory cell can be RESET directly to the state having the next highest resistance. Program conditions, such as pulse width and/or magnitude, may depend on the state to which the memory cell is being SET. A higher energy can be used for programming higher current states.Type: ApplicationFiled: September 12, 2013Publication date: March 12, 2015Applicant: SanDisk 3D LLCInventors: Abhijit Bandyopadhyay, Roy E. Scheuerlein, Chandrasekhar R. Gorla, Brian Le
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Patent number: D751813Type: GrantFiled: January 31, 2014Date of Patent: March 22, 2016Assignee: Zero Chroma, LLCInventors: Brian Le Gette, David Reeb