Abstract: Spontaneous preterm birth (sPTB) is premature delivery prior to 37 weeks of pregnancy and is a leading cause of infant mortality worldwide. sPTB is associated with a unique gene expression profile. Identified herein are numerous safe and proven therapeutic compositions used for unrelated indications that have the biological effect of reversing, in part, the gene expression profile of sPTB and which can be used in preventative or interventional treatments to prevent, delay, or ameliorate sPTB. The repurposed drugs include several Class A and Class B therapeutics that are regarded as safe or low risk in pregnant subjects.

Abstract: Spontaneous preterm birth (sPTB) is premature delivery prior to 37 weeks of pregnancy and is a leading cause of infant mortality worldwide. sPTB is associated with a unique gene expression profile. Identified herein are numerous safe and proven therapeutic compositions used for unrelated indications that have the biological effect of reversing, in part, the gene expression profile of sPTB and which can be used in preventative or interventional treatments to prevent, delay, or ameliorate sPTB. The repurposed drugs include several Class A and Class B therapeutics that are regarded as safe or low risk in pregnant subjects.

Abstract: Systems and methods for magnetic induction of a penile prosthesis are disclosed. The magnetic induction system includes a wand that has a coil arrangement covered with a thermal and electrical insulator sheath operable to generate an alternating magnetic field. The coil arrangement of the sheath is configured to receive the length of the penile prosthesis therein. The penile prosthesis may be made from a shape memory material such that application of alternating magnetic fields generated by the magnetic induction system induces eddy currents that raise the temperature of the penile prosthesis to a temperature above the austenitic transformation temperature that allows the penile prosthesis to achieve an erect state.

Abstract: A monolithic three-dimensional memory array is provided that includes a plurality of global bit lines disposed above a substrate, a plurality of vertically-oriented bit lines disposed above the global bit lines, a plurality of word lines disposed above the global bit lines, a plurality of memory cells coupled between the vertically-oriented bit lines and the word lines, and a plurality of isolation elements coupled between the vertically-oriented bit lines and the global bit lines. Each isolation element includes a vertical thin-film transistor and a threshold selector device.

Abstract: A monolithic three-dimensional memory array is provided that includes a plurality of global bit lines disposed above a substrate, a plurality of vertically-oriented bit lines disposed above the global bit lines, a plurality of word lines disposed above the global bit lines, a plurality of memory cells coupled between the vertically-oriented bit lines and the word lines, and a plurality of isolation elements coupled between the vertically-oriented bit lines and the global bit lines. Each isolation element includes a vertical thin-film transistor and a threshold selector device.

Abstract: A method is provided that includes forming a memory cell that includes a memory element coupled in series with an isolation element. The isolation element includes a vertical thin-film transistor and a threshold selector device.

Abstract: A method, a system, and an article are provided for managing a scrolling operation on a computer display. An example method can include: providing a plurality of cells for presenting graphical elements on a user device; advancing a sequence of the cells through a visible area on a display of the user device; moving a first cell that is no longer within the visible area to one of a plurality of cell recycle pools; moving a second cell from one of the plurality of cell recycle pools to a cell generation area; generating a graphical element for the second cell within the cell generation area; and advancing the second cell from the cell generation area into the visible area on the display of the user device.

Abstract: A method is provided that includes forming a bit line above a substrate; forming a word line above the substrate, and forming a non-volatile memory cell between the bit line and the word line. The non-volatile memory cell includes a non-volatile memory material coupled in series with an isolation element. The isolation element includes a first electrode, a second electrode, and a semiconductor layer and a barrier layer disposed between the first electrode and the second electrode.

Abstract: Systems and methods for magnetic induction of a penile prosthesis are disclosed. The magnetic induction system includes a wand that has a coil arrangement covered with a thermal and electrical insulator sheath operable to generate an alternating magnetic field. The coil arrangement of the sheath is configured to receive the length of the penile prosthesis therein. The penile prosthesis may be made from a shape memory material such that application of alternating magnetic fields generated by the magnetic induction system induces eddy currents that raise the temperature of the penile prosthesis to a temperature above the austenitic transformation temperature that allows the penile prosthesis to achieve an erect state.

Abstract: Systems and methods for magnetic induction of a penile prosthesis are disclosed. The magnetic induction system includes a wand that has a coil arrangement covered with a thermal and electrical insulator sheath operable to generate an alternating magnetic field. The coil arrangement of the sheath is configured to receive the length of the penile prosthesis therein. The penile prosthesis may be made from a shape memory material such that application of alternating magnetic fields generated by the magnetic induction system induces eddy currents that raise the temperature of the penile prosthesis to a temperature above the austenitic transformation temperature that allows the penile prosthesis to achieve an erect state.

Abstract: A method is provided that includes forming a bit line above a substrate; forming a word line above the substrate, and forming a non-volatile memory cell between the bit line and the word line. The non-volatile memory cell includes a non-volatile memory material coupled in series with an isolation element. The isolation element includes a first electrode, a second electrode, and a semiconductor layer and a barrier layer disposed between the first electrode and the second electrode.

Abstract: Systems and methods for magnetic induction of a penile prosthesis are disclosed. The magnetic induction system includes a wand that has a coil arrangement covered with a thermal and electrical insulator sheath operable to generate an alternating magnetic field. The coil arrangement of the sheath is configured to receive the length of the penile prosthesis therein. The penile prosthesis may be made from a shape memory material such that application of alternating magnetic fields generated by the magnetic induction system induces eddy currents that raise the temperature of the penile prosthesis to a temperature above the austenitic transformation temperature that allows the penile prosthesis to achieve an erect state.

Abstract: Operating ReRAM memory is disclosed herein. The memory cells may be trained prior to initially programming them. The training may help to establish a percolation path. In some aspects, a transistor limits current of the memory cell when training and programming. A higher current limit is used during training, which conditions the memory cell for better programming. The non-memory may be operated in unipolar mode. The memory cells can store multiple bits per memory cell. A memory cell can be SET directly from its present state to one at least two data states away. A memory cell can be RESET directly to the state having the next highest resistance. Program conditions, such as pulse width and/or magnitude, may depend on the state to which the memory cell is being SET. A higher energy can be used for programming higher current states.

Abstract: Operating ReRAM memory is disclosed herein. The memory cells may be trained prior to initially programming them. The training may help to establish a percolation path. In some aspects, a transistor limits current of the memory cell when training and programming. A higher current limit is used during training, which conditions the memory cell for better programming. The non-memory may be operated in unipolar mode. The memory cells can store multiple bits per memory cell. A memory cell can be SET directly from its present state to one at least two data states away. A memory cell can be RESET directly to the state having the next highest resistance. Program conditions, such as pulse width and/or magnitude, may depend on the state to which the memory cell is being SET. A higher energy can be used for programming higher current states.

Abstract: Operating ReRAM memory is disclosed herein. The memory cells may be trained prior to initially programming them. The training may help to establish a percolation path. In some aspects, a transistor limits current of the memory cell when training and programming. A higher current limit is used during training, which conditions the memory cell for better programming. The non-memory may be operated in unipolar mode. The memory cells can store multiple bits per memory cell. A memory cell can be SET directly from its present state to one at least two data states away. A memory cell can be RESET directly to the state having the next highest resistance. Program conditions, such as pulse width and/or magnitude, may depend on the state to which the memory cell is being SET. A higher energy can be used for programming higher current states.

Abstract: Operating ReRAM memory is disclosed herein. The memory cells may be trained prior to initially programming them. The training may help to establish a percolation path. In some aspects, a transistor limits current of the memory cell when training and programming. A higher current limit is used during training, which conditions the memory cell for better programming. The non-memory may be operated in unipolar mode. The memory cells can store multiple bits per memory cell. A memory cell can be SET directly from its present state to one at least two data states away. A memory cell can be RESET directly to the state having the next highest resistance. Program conditions, such as pulse width and/or magnitude, may depend on the state to which the memory cell is being SET. A higher energy can be used for programming higher current states.

Abstract: Non-volatile storage devices having reversible resistance storage elements are disclosed herein. In one aspect, a memory cell unit includes one or more memory cells and a transistor (e.g., FET) that is used to control (e.g., limit) current of the memory cells. The drain of the transistor may be connected to a first end of the memory cell. If the memory cell unit has multiple memory cells then the drain may be connected to a node that is common to a first end of each of the memory cells. The source of the transistor is connected to a common source line. The gate of the transistor may be connected to a word line. The same word line may connect to the transistor gate of several (or many) different memory cell units. A second end of the memory cell is connected to a bit line.

Abstract: A method of forming a memory cell is provided, the method including forming a diode including a first region having a first conductivity type, counter-doping the diode to change the first region to a second conductivity type, and forming a memory element coupled in series with the diode. Other aspects are also provided.

Abstract: A method and system for forming, resetting, or setting memory cells is disclosed. One or more programming conditions to apply to a memory cell having a reversible resistivity-switching element may be determined based on its resistance. The determination of one or more programming conditions may also be based on a pre-determined algorithm that may be based on properties of the memory cell. The one or more programming conditions may include a programming voltage and a current limit. For example, the magnitude of the programming voltage may be based on the resistance. As another example, the width of a programming voltage pulse may be based on the resistance. In some embodiments, a current limit used during programming is determined based on the memory cell resistance.

Abstract: A method and system for forming reversible resistivity-switching elements is described herein. Forming refers to reducing the resistance of the reversible resistivity-switching element, and is generally understood to refer to reducing the resistance for the first time. Prior to forming the reversible resistivity-switching element it may be in a high-resistance state. A first voltage is applied to “partially form” the reversible resistivity-switching element. The first voltage has a first polarity. Partially forming the reversible resistivity-switching element lowers the resistance of the reversible resistivity-switching element. A second voltage that has the opposite polarity as the first is then applied to the reversible resistivity-switching element. Application of the second voltage may further lower the resistance of the reversible resistivity-switching element. Therefore, the second voltage could be considered as completing the forming of the reversible resistivity-switching element.