Abstract: An enhanced performance differential output amplifier and differential amplification method are provided. The amplifier comprises a first transistor to accept a single-ended input signal and supply a first output signal, and a second transistor to supply a second output signal, approximately 180 degrees out of phase from the first output signal. A first capacitor is connected between the base of the first transistor and the emitter of the second transistor. A second capacitor is connected between the emitter of the first transistor and first voltage. At least one emitter resistor, but typically two, is connected between the emitters of the first and second transistors, and a current source. The collectors of the first and second transistors are operatively connected to the first voltage, typically through resistors. The current source is connected between the emitter resistors and a second voltage (Vee) having a lower potential than the first voltage.

Abstract: A digital phase detector in accordance with the present invention is capable of stable high speed operation. The phase detector operates in a half-rate manner, i.e., the digital clock frequency is one-half the digital data rate. A phase adjustment signal is generated with digital logic elements in a manner that reduces the timing requirements of the digital devices. The phase adjustment signal contains phase reference pulses having pulsewidths that are greater than or equal to the pulsewidth associated with the digital clock signal. The use of relatively wide phase reference pulses reduces the likelihood of instability and erroneous detection due to circuit speed limitations, thus resulting in an overall increase in detector performance.

Abstract: A system and method are provided for compensating a comparator threshold level. The method comprises: accepting an input signal with an ac component; lowpass filtering the input signal to generate the input signal average voltage; accepting the input signal average voltage; accepting a first dc level; summing the average voltage with the first dc level; supplying a first sum as a first comparator threshold level; comparing the input signal to the first comparator threshold level; and, supplying a first comparator output signal with an ac component. In some aspects of the method, accepting a first dc level includes accepting a plurality of dc levels. Then, the average voltage is summed with each of the plurality of dc levels and supplied as a corresponding plurality of comparator threshold levels. The input signal is compared to each of the comparator threshold levels and a plurality of comparator output signals are supplied.

Abstract: A ring oscillator integrated circuit is provided that is comprised of a plurality of parallely arranged ring oscillator sections, where a ring oscillator section can be any conventional ring oscillator circuit. That is, the inputs and the outputs of a plurality of conventional ring oscillators are connected together. Since each ring oscillator section output signal includes random noise, the parallel arrangement of ring oscillators, and the summing of several oscillator signals, causes at least some noise cancellation. As a result, a lower noise oscillator signal is supplied. A method of reducing random noise in a ring oscillator circuit is also provided.

Abstract: A differential signal current-mode logic (CML) circuit is provided which provides an equal delay output. Convention differential logic CML circuits have upper stage and lower stage transistors pairs. Input signals that are provided to the lower stage are necessarily delayed with respect to inputs provided to the upper stage. The present invention provides parallel upper stage sections so that each input signal is translated to the output through the same number of transistors. Thus, the delay associated with each input signal is made equal. Specific examples of exclusive OR, OR, and AND circuits are provided.