Patents by Inventor Brian Lee Eastep

Brian Lee Eastep has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Completely encapsulated top electrode of a ferroelectric capacitor using a lead-enhanced encapsulation layer
    Patent number: 6281023
    Abstract: A ferroelectric capacitor includes a bottom electrode, a top electrode, and a ferroelectric layer located between the top and bottom electrodes that extends to completely encapsulate the top electrode, except for a contact hole to allow metalization of the top electrode. The total encapsulation of the top electrode reduces the sensitivity of the ferroelectric capacitor to hydrogen and thus improves electrical switching performance.
    Type: Grant
    Filed: January 11, 2001
    Date of Patent: August 28, 2001
    Assignee: Ramtron International Corporation
    Inventors: Brian Lee Eastep, Thomas A. Evans
  • Completely encapsulated top electrode of a ferroelectric capacitor using a lead-enhanced encapsulation layer
    Publication number: 20010001488
    Abstract: A ferroelectric capacitor includes a bottom electrode, a top electrode, and a ferroelectric layer located between the top and bottom electrodes that extends to completely encapsulate the top electrode, except for a contact hole to allow metalization of the top electrode. The total encapsulation of the top electrode reduces the sensitivity of the ferroelectric capacitor to hydrogen and thus improves electrical switching performance.
    Type: Application
    Filed: January 11, 2001
    Publication date: May 24, 2001
    Inventors: Brian Lee Eastep, Thomas A. Evans
  • Completely encapsulated top electrode of a ferroelectric capacitor using a lead-enhanced escapsulation layer
    Patent number: 6211542
    Abstract: A ferroelectric capacitor includes a bottom electrode, a top electrode, and a ferroelectric layer located between the top and bottom electrodes that extends to completely encapsulate the top electrode, except for a contact hole to allow metalization of the top electrode. The total encapsulation of the top electrode reduces the sensitivity of the ferroelectric capacitor to hydrogen and thus improves electrical switching performance.
    Type: Grant
    Filed: May 27, 1998
    Date of Patent: April 3, 2001
    Assignee: Ramtron International Corporation
    Inventors: Brian Lee Eastep, Thomas A. Evans
  • Multi-layer approach for optimizing ferroelectric film performance
    Patent number: 6090443
    Abstract: A multi-layer ferroelectric thin film includes a nucleation layer, a bulk layer, and an optional cap layer. A thin nucleation layer of a specific composition is implemented on a bottom electrode to optimize ferroelectric crystal orientation and is markedly different from the composition required in the bulk of a ferroelectric film. The bulk film utilizes the established nucleation layer as a foundation for its crystalline growth. A multi-step deposition process is implemented to achieve a desired composition profile. This method also allows for an optional third composition adjustment near the upper surface of the film to ensure compatibility with an upper electrode interface and to compensate for interactions resulting from subsequent processing.
    Type: Grant
    Filed: April 22, 1998
    Date of Patent: July 18, 2000
    Assignee: Ramtron International Corporation
    Inventor: Brian Lee Eastep
  • Multi-layer approach for optimizing ferroelectric film performance
    Patent number: 6080499
    Abstract: A multi-layer ferroelectric thin film includes a nucleation layer, a bulk layer, and an optional cap layer. A thin nucleation layer of a specific composition is implemented on a bottom electrode to optimize ferroelectric crystal orientation and is markedly different from the composition required in the bulk of a ferroelectric film. The bulk film utilizes the established nucleation layer as a foundation for its crystalline growth. A multi-step deposition process is implemented to achieve a desired composition profile. This method also allows for an optional third composition adjustment near the upper surface of the film to ensure compatibility with an upper electrode interface and to compensate for interactions resulting from subsequent processing.
    Type: Grant
    Filed: July 18, 1997
    Date of Patent: June 27, 2000
    Assignee: Ramtron International Corporation
    Inventor: Brian Lee Eastep