Abstract: Embodiments herein provide for avoiding address collisions in a memory device. In one embodiment, a memory controller includes a command scheduler operable to process a read-modify-write I/O command to a location in memory, to detect another I/O command to the same memory location while the read-modify-write I/O command is accessing the memory location, and to stall the other I/O command until the read-modify-write I/O command is complete while allowing a third I/O command to access the memory.

Abstract: Embodiments herein provide for avoiding address collisions in a memory device. In one embodiment, a memory controller includes a command scheduler operable to process a read-modify-write I/O command to a location in memory, to detect another I/O command to the same memory location while the read-modify-write I/O command is accessing the memory location, and to stall the other I/O command until the read-modify-write I/O command is complete while allowing a third I/O command to access the memory.

Abstract: Embodiments herein provide for avoiding ID collisions in a memory device. In one embodiment, a memory device includes slave logic operable to receive I/O commands from a plurality of master components and a memory controller operable to process the I/O commands from the master components to operate on data in the memory. Each I/O command comprises an ID assigned by its originating master component. The slave logic is further operable to determine the ID of a first I/O command from a first of the master components, to receive a second I/O command from a second of the master components having a same ID as the first I/O command while the first I/O command is being processed by the memory controller, and to stall the second I/O command until the first I/O command is complete while allowing other I/O commands with other IDs to access the memory.

Abstract: Disclosed is a system and method for monitoring PCIe packets between clock domains. An interrupt is set to a root complex or external hardware based on the detection of malformed, and illegal, packets.

Abstract: Disclosed is a system and method for monitoring PCIe packets between clock domains. An interrupt is set to a root complex or external hardware based on the detection of malformed, and illegal, packets.

Abstract: Methods and structure for accounting are provided for enhancing communications via a PCIE bridge. The bridge comprises a host interface that manages communications with a host device, and a PCIE interface that provides Memory Read Requests (MRds) to a PCIE device and receives Memory Read Completions (MRCs) from the PCIE device. The bridge also comprises a control unit that inserts tag information into the MRds. The control unit detects a reset of the host interface and revises the tag information inserted into the MRds responsive to detecting the reset. Additionally, the control unit analyzes tag information of received MRCs to determine whether it is the revised tag information or is old tag information, returns completion data from MRCs having the revised tag information to the host device, and discards completion data from received MRCs having the old tag information.

Abstract: Methods and structure for accounting are provided for enhancing communications via a PCIE bridge. The bridge comprises a host interface that manages communications with a host device, and a PCIE interface that provides Memory Read Requests (MRds) to a PCIE device and receives Memory Read Completions (MRCs) from the PCIE device. The bridge also comprises a control unit that inserts tag information into the MRds. The control unit detects a reset of the host interface and revises the tag information inserted into the MRds responsive to detecting the reset. Additionally, the control unit analyzes tag information of received MRCs to determine whether it is the revised tag information or is old tag information, returns completion data from MRCs having the revised tag information to the host device, and discards completion data from received MRCs having the old tag information.