Patents by Inventor Brian Leung

Brian Leung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11928512
    Abstract: A reconfigurable data processor comprises an array of configurable units configurable to allocate a plurality of sets of configurable units in the array to implement respective execution fragments of the data processing operation. Quiesce logic is coupled to configurable units in the array, configurable to respond to a quiesce control signal to quiesce the sets of configurable units in the array on quiesce boundaries of the respective execution fragments, and to forward quiesce ready signals for the respective execution fragments when the corresponding sets of processing units are ready. An array quiesce controller distributes the quiesce control signal to configurable units in the array, and receives quiesce ready signals for the respective execution fragments from the quiesce logic.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: March 12, 2024
    Assignee: SambaNova Systems, Inc.
    Inventors: Raghu Prabhakar, Manish K. Shah, Pramod Nataraja, David Brian Jackson, Kin Hing Leung, Ram Sivaramakrishnan, Sumti Jairath, Gregory Frederick Grohoski
  • Patent number: 11656662
    Abstract: Embodiments herein may present an integrated circuit or a computing system having an integrated circuit, where the integrated circuit includes a physical network layer, a physical computing layer, and a physical memory layer, each having a set of dies, and a die including multiple tiles. The physical network layer further includes one or more signal pathways dynamically configurable between multiple pre-defined interconnect topologies for the multiple tiles, where each topology of the multiple pre-defined interconnect topologies corresponds to a communication pattern related to a workload. At least a tile in the physical computing layer is further arranged to move data to another tile in the physical computing layer or a storage cell of the physical memory layer through the one or more signal pathways in the physical network layer. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: February 11, 2021
    Date of Patent: May 23, 2023
    Assignee: Intel Corporation
    Inventors: Simon C. Steely, Jr., Richard Dischler, David Bach, Olivier Franza, William J. Butera, Christian Karl, Benjamin Keen, Brian Leung
  • Publication number: 20210255674
    Abstract: Embodiments herein may present an integrated circuit or a computing system having an integrated circuit, where the integrated circuit includes a physical network layer, a physical computing layer, and a physical memory layer, each having a set of dies, and a die including multiple tiles. The physical network layer further includes one or more signal pathways dynamically configurable between multiple pre-defined interconnect topologies for the multiple tiles, where each topology of the multiple pre-defined interconnect topologies corresponds to a communication pattern related to a workload. At least a tile in the physical computing layer is further arranged to move data to another tile in the physical computing layer or a storage cell of the physical memory layer through the one or more signal pathways in the physical network layer. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: February 11, 2021
    Publication date: August 19, 2021
    Inventors: Simon C. Steely, JR., Richard Dischler, David Bach, Olivier Franza, William J. Butera, Christian Karl, Benjamin Keen, Brian Leung
  • Patent number: 10963022
    Abstract: Embodiments herein may present an integrated circuit or a computing system having an integrated circuit, where the integrated circuit includes a physical network layer, a physical computing layer, and a physical memory layer, each having a set of dies, and a die including multiple tiles. The physical network layer further includes one or more signal pathways dynamically configurable between multiple pre-defined interconnect topologies for the multiple tiles, where each topology of the multiple pre-defined interconnect topologies corresponds to a communication pattern related to a workload. At least a tile in the physical computing layer is further arranged to move data to another tile in the physical computing layer or a storage cell of the physical memory layer through the one or more signal pathways in the physical network layer. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: March 30, 2021
    Assignee: Intel Corporation
    Inventors: Simon C. Steely, Jr., Richard Dischler, David Bach, Olivier Franza, William J. Butera, Christian Karl, Benjamin Keen, Brian Leung
  • Publication number: 20200371566
    Abstract: Embodiments herein may present an integrated circuit or a computing system having an integrated circuit, where the integrated circuit includes a physical network layer, a physical computing layer, and a physical memory layer, each having a set of dies, and a die including multiple tiles. The physical network layer further includes one or more signal pathways dynamically configurable between multiple pre-defined interconnect topologies for the multiple tiles, where each topology of the multiple pre-defined interconnect topologies corresponds to a communication pattern related to a workload. At least a tile in the physical computing layer is further arranged to move data to another tile in the physical computing layer or a storage cell of the physical memory layer through the one or more signal pathways in the physical network layer. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: April 29, 2020
    Publication date: November 26, 2020
    Inventors: Simon C. Steely, JR., Richard Dischler, David Bach, Olivier Franza, William J. Butera, Christian Karl, Benjamin Keen, Brian Leung
  • Patent number: 10691182
    Abstract: Embodiments herein may present an integrated circuit or a computing system having an integrated circuit, where the integrated circuit includes a physical network layer, a physical computing layer, and a physical memory layer, each having a set of dies, and a die including multiple tiles. The physical network layer further includes one or more signal pathways dynamically configurable between multiple pre-defined interconnect topologies for the multiple tiles, where each topology of the multiple pre-defined interconnect topologies corresponds to a communication pattern related to a workload. At least a tile in the physical computing layer is further arranged to move data to another tile in the physical computing layer or a storage cell of the physical memory layer through the one or more signal pathways in the physical network layer. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: June 23, 2020
    Assignee: Intel Corporation
    Inventors: Simon C. Steely, Jr., Richard Dischler, David Bach, Olivier Franza, William J. Butera, Christian Karl, Benjamin Keen, Brian Leung
  • Publication number: 20190354146
    Abstract: Embodiments herein may present an integrated circuit or a computing system having an integrated circuit, where the integrated circuit includes a physical network layer, a physical computing layer, and a physical memory layer, each having a set of dies, and a die including multiple tiles. The physical network layer further includes one or more signal pathways dynamically configurable between multiple pre-defined interconnect topologies for the multiple tiles, where each topology of the multiple pre-defined interconnect topologies corresponds to a communication pattern related to a workload. At least a tile in the physical computing layer is further arranged to move data to another tile in the physical computing layer or a storage cell of the physical memory layer through the one or more signal pathways in the physical network layer. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: May 20, 2019
    Publication date: November 21, 2019
    Inventors: Simon C. Steely, JR., Richard Dischler, David Bach, Olivier Franza, William J. Butera, Christian Karl, Benjamin Keen, Brian Leung
  • Publication number: 20190130424
    Abstract: A system and method to provide a sentiment measurement system with automatic ad placement to collect surveys of voters is described. This enables a candidate to rapidly and easily measure voter sentiment at scale, quickly and cost-effectively while addressing technical limitations that normally prevent accurate use of traditional internet ad platforms for such purposes. Existing ad targeting is not designed for providing representative samples, thus the system can automatically target ads and regularly adjust based on incoming poll responses to ensure representative data is received. The system and method applies to other sentiment measurement, e.g. general opinion polling. Further, the system and method combines online micro-targeting with dynamic bias correction to produce appropriate sample groups.
    Type: Application
    Filed: October 26, 2018
    Publication date: May 2, 2019
    Applicant: CHANGE RESEARCH, PUBLIC BENEFIT CORPORATION
    Inventors: Michael GREENFIELD, Jonathan GOLDMAN, Benjamin GREENFIELD, Christopher COKE, Lucia ZHENG, Brian LEUNG
  • Publication number: 20190044889
    Abstract: Particular embodiments described herein provide for an electronic device that can be configured to group two or more small packets that are to be communicated to a common destination, where the two or more packets are grouped together in a queue dedicated to temporarily store small packets that are to be communicated to the common destination, coalesce the small packets into a coalesced packet, where the coalesced packet is a network packet, and communicate the coalesced packet to the common destination. In an example, the size of a small packet is a packet that is smaller than the network packet. In another example, the size of a small packet is less than half the size of the network packet.
    Type: Application
    Filed: June 29, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Olivier Sylvain Gerard Serres, Venkata S. Krishnan, Brian Leung, Chyi-Chang Miao, Lawrence Colm Stewart
  • Patent number: 7881534
    Abstract: Various technologies and techniques are disclosed for using user corrections to help improve handwriting recognition operations. The system tracks user corrections to recognition results. The system receives handwritten input from the user and performs a recognition operation to determine a top recognized word. The prior corrections made by the user are analyzed to calculate a ratio of times the user has corrected the top recognized word to a particular other word as opposed to correcting the particular other word to the top recognized word. If the ratio meets or exceeds a required minimum, then at least one secondary source is optionally analyzed to determine if the particular other word is used a certain number of times more frequently than the top recognized word in the secondary source. The system performs a swap of the top recognized word with the particular other word when the required criteria are met.
    Type: Grant
    Filed: June 19, 2006
    Date of Patent: February 1, 2011
    Assignee: Microsoft Corporation
    Inventors: Brian Leung, Michael Revow, Richard K. Sailor
  • Patent number: 7813920
    Abstract: Learning to reorder alternates based on a user's personalized vocabulary may be provided. An alternate list provided to a user for replacing words input by the user via a character recognition application may be reordered based on data previously viewed or input by the user (personal data). The alternate list may contain generic data, for example, words for possible substitution with one or more words input by the user. By using the user's personal data and statistical learning methodologies in conjunction with generic data in the alternate list, the alternate list can be reordered to present a top alternate that more closely reflect the user's vocabulary. Accordingly, the user is presented with a top alternate that is more likely to be used by the user to replace data incorrectly input.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: October 12, 2010
    Assignee: Microsoft Corporation
    Inventors: Brian Leung, Michael Revow
  • Publication number: 20090006095
    Abstract: Learning to reorder alternates based on a user's personalized vocabulary may be provided. An alternate list provided to a user for replacing words input by the user via a character recognition application may be reordered based on data previously viewed or input by the user (personal data). The alternate list may contain generic data, for example, words for possible substitution with one or more words input by the user. By using the user's personal data and statistical learning methodologies in conjunction with generic data in the alternate list, the alternate list can be reordered to present a top alternate that more closely reflect the user's vocabulary. Accordingly, the user is presented with a top alternate that is more likely to be used by the user to replace data incorrectly input.
    Type: Application
    Filed: June 29, 2007
    Publication date: January 1, 2009
    Inventors: Brian Leung, Michael Revow
  • Publication number: 20080294982
    Abstract: A processing device, such as, for example, a tablet PC, or other processing device, may receive non-textual language input. The non-textual language input may be recognized to produce one or more textual characters. The processing device may generate a list including one or more prefixes based on the produced one or more textual characters. Multiple text auto-completion predictions may be generated based on multiple prediction data sources and the one or more prefixes. The multiple text auto-completion predictions may be ranked and sorted based on features associated with each of the text auto-completion predictions. The processing device may present a predetermined number of best text auto-completion predictions. A selection of one of the presented predetermined number of best text auto completion predictions may result in a word, currently being entered, being replaced by the selected one of the predetermined number of best text auto completion predictions.
    Type: Application
    Filed: May 21, 2007
    Publication date: November 27, 2008
    Applicant: Microsoft Corporation
    Inventors: Brian Leung, Qi Zhang
  • Publication number: 20080276318
    Abstract: A spam detection system employs a “Delayed-Verification on Purported Responsible Address” (DVPRA) module which verifies the validity of the return address of a received e-mail message in mail server in a time delay interval specifiable by the user. An implementation of the module as a Spam Mail Filter in a stand-alone spam detection system. An implementation of the module as a supplementary to the existing anti-spam systems.
    Type: Application
    Filed: May 2, 2007
    Publication date: November 6, 2008
    Inventors: Brian Leung, Keith Lau, Wah Cheong Hui, Ching Shan Wong
  • Patent number: 7369702
    Abstract: Input handwritten characters are classified as print or cursive based upon numerical feature values calculated from the shape of an input character. The feature values are applied to inputs of an artificial neural network which outputs a probability of the input character being print or cursive. If a character is classified as print, it is analyzed by a print character recognizer. If a character is classified as cursive, it is analyzed using a cursive character recognizer. The cursive character recognizer compares the input character to multiple prototype characters using a Dynamic Time Warping (DTW) algorithm.
    Type: Grant
    Filed: November 7, 2003
    Date of Patent: May 6, 2008
    Assignee: Microsoft Corporation
    Inventors: Ahmad A. Abdulkader, Brian Leung, Henry Allan Rowley, Qi Zhang
  • Publication number: 20070292031
    Abstract: Various technologies and techniques are disclosed for using user corrections to help improve handwriting recognition operations. The system tracks user corrections to recognition results. The system receives handwritten input from the user and performs a recognition operation to determine a top recognized word. The prior corrections made by the user are analyzed to calculate a ratio of times the user has corrected the top recognized word to a particular other word as opposed to correcting the particular other word to the top recognized word. If the ratio meets or exceeds a required minimum, then at least one secondary source is optionally analyzed to determine if the particular other word is used a certain number of times more frequently than the top recognized word in the secondary source. The system performs a swap of the top recognized word with the particular other word when the required criteria are met.
    Type: Application
    Filed: June 19, 2006
    Publication date: December 20, 2007
    Applicant: Microsoft Corporation
    Inventors: Brian Leung, Michael Revow, Richard K. Sailor
  • Publication number: 20050100217
    Abstract: Input handwritten characters are classified as print or cursive based upon numerical feature values calculated from the shape of an input character. The feature values are applied to inputs of an artificial neural network which outputs a probability of the input character being print or cursive. If a character is classified as print, it is analyzed by a print character recognizer. If a character is classified as cursive, it is analyzed using a cursive character recognizer. The cursive character recognizer compares the input character to multiple prototype characters using a Dynamic Time Warping (DTW) algorithm.
    Type: Application
    Filed: November 7, 2003
    Publication date: May 12, 2005
    Applicant: Microsoft Corporation
    Inventors: Ahmad Abdulkader, Brian Leung, Henry Rowley, Qi Zhang
  • Publication number: 20030220834
    Abstract: A Retail Loyalty System for retailers to create and sustain customer loyalty and repeat purchases, that is layered over the Internet, and utilizes the Smart Card technology to store the loyalty points and personal information; built-in Ethernet and TCP/IP Network Interface and built-in Embedded Web Server allow web-based administration; a network terminal allows the shoppers to check their loyalty points in real-time manner, and allows the shoppers to select the reward items to redeem on the LCD display with touch-screen panel; a POS Add-in Module to allow adding the loyalty points earned by the purchase transaction, and to allow deducting the loyalty points resulted by redeeming reward items. The reward scheme may be updated & readjusted remotely by the computer at the head office via the Internet, and may be synchronized across all the branches of the retailer. Optionally, all the transaction logs can be uploaded to a centralized CRM database server for CPM (Customer Relationship Management) purpose.
    Type: Application
    Filed: May 21, 2002
    Publication date: November 27, 2003
    Inventors: Brian Leung, Wah-Cheong Hui
  • Patent number: 6643779
    Abstract: A security system includes a network adapter that links the security system to a computer network infrastructure to establish a connection to the network. An embedded HTTP server receives and responses to the requests sent from any HTTP client having access to the computer network. A browser-based management module allows any HTTP client that is capable of accessing the computer network to setup and maintain the security system. A browser-based information query module allows any HTTP client that is capable to access the computer network to access the information of the security system.
    Type: Grant
    Filed: April 15, 1999
    Date of Patent: November 4, 2003
    Inventors: Brian Leung, Wah Cheong Hui