Abstract: An offset weight bar is provided which operates with the lifter's neuro-fascial connections to increase muscle activation and recruitment of muscle groups. The offset weight bar includes a grip portion that is shaped in accordance with the meuro-fascial connections in the lifter's hands and arms. The offset weight bar also offsets the weight of the bar from the lifter's palm to a point out along the lifter's unfolded fingers. The shape of the offset weight bar operates with the offset of the weight from the palm to increase the lifter's muscle activation and muscle group recruitment in accordance with the lifter's neuro-fascial physiology.

Abstract: A method and architecture for improving the usability and manufacturing yield of a microprocessor having a large on-chip n-way set associative cache. The architecture provides a method for working around defects in the portion of the die allocated to the data array of the cache. In particular, by adding a plurality of muxes to a way or ways in the data array of an associative cache having the shorter paths to the access control logic, each way in a bank can be selectively replaced or remapped to the ways with the shorter paths without adding any latency to the system. This selective remapping of separate ways in individual banks of the set associative cache provides a more efficient way to absorb defects and allows more defects to be absorbed in the data array of a set associative cache.

Abstract: A method and architecture for improving the usability and manufacturing yield of a microprocessor having a large on-chip n-way set associative cache. The architecture provides a method for working around defects in the portion of the die allocated to the data array of the cache. In particular, by adding a plurality of muxes to a way or ways in the data array of an associative cache having the shorter paths to the access control logic, each way in a bank can be selectively replaced or remapped to the ways with the shorter paths without adding any latency to the system. This selective remapping of separate ways in individual banks of the set associative cache provides a more efficient way to absorb defects and allows more defects to be absorbed in the data array of a set associative cache.

Abstract: A computer system has a set-associative, multi-way cache system, in which at least one way is designated as a fast lane, and remaining way(s) are designated slow lanes. Any data that needs to be loaded into cache, but is not likely to be needed again in the future, preferably is loaded into the fast lane. Data loaded into the fast lane is earmarked for immediate replacement. Data loaded into the slow lanes preferably is data that may not needed again in the near future. Slow data is kept in cache to permit it to be reused if necessary. The high-performance mechanism of data access in a modem microprocessor is with a prefetch; data is moved, with a special prefetch instruction, into cache prior to its intended use. The prefetch instruction requires less machine resources, than carrying out the same intent with an ordinary load instruction. So, the slow-lane, fast-lane decision is accomplished by having a multiplicity of prefetch instructions.

Abstract: A method and architecture for improving the usability and manufacturing yield of a microprocessor having a large on-chip n-way set associative cache. The architecture provides a method for working around defects in the portion of the die allocated to the data array of the cache. In particular, by adding a plurality of muxes to a way or ways in the data array of an associative cache having the shorter paths to the access control logic, each way in a bank can be selectively replaced or remapped to the ways with the shorter paths without adding any latency to the system. This selective remapping of separate ways in individual banks of the set associative cache provides a more efficient way to absorb defects and allows more defects to be absorbed in the data array of a set associative cache.

Abstract: A computer system has a plurality of processors wherein each processor preferably has its own cache memory. Each processor or group of processors may have a memory controller that interfaces to a main memory. Each main memory includes a “directory” that maintains the directory coherence state of each block of that memory. One or more of the processors are members of a “local” group of processors. Processors outside a local group are referred to as “remote” processors with respect to that local group. Whenever a remote processor performs a memory reference for a particular block of memory, the processor that maintains the directory for that block normally updates the directory to reflect that the remote processor now has exclusive ownership of the block. However, memory references between processors within a local group do not result in directory writes.