Abstract: A computer-based software task management system includes an index register configured to store a data register pointer for pointing to a data register. A Task ID register is coupled to the index register and configured to store a Task ID keyed to the index register. A Task ID memory is coupled to the Task ID register and configured to store a flag indicating whether the Task ID is available. A state machine is coupled to the Task ID memory and configured to allocate Task IDs on an available basis using a task ID memory.

Abstract: A computer-based software task management system (100) includes an index register (130) configured to store a data register pointer for pointing to a data register (150). A Task ID register (110) is coupled to the index register and configured to store a Task ID keyed to the index register. A Task ID memory (120) is coupled to the Task ID register and configured to store a flag indicating whether the Task ID is available. A state machine (105) is coupled to the Task ID memory and configured to allocate Task IDs on an available basis using a Task ID memory. Advantages of the invention include the ability to efficiently manage a multithreaded operating system with virtually no additional software overhead.

Abstract: Various enhancements may be made to a DMA controller to optimize the DMA controller for use in non-uniform DMA applications such as Universal Serial Bus (USB) applications. First, a DMA count register that is used to store a count value that controls the length of a data transfer over a DMA channel may be capable of being selectively disabled, such that when the DMA count register is disabled, a DMA control circuit may perform a data transfer independent of the DMA count register. An endpoint watchdog timer may also be coupled to a DMA control circuit and configured to generate an interrupt if no data is received by the DMA channel within a predetermined period of time. In addition, a DMA control circuit may incorporate partial word hold off functionality to delay transmission of a final word of data from a data packet if the final word is a partial word.

Abstract: A system for preventing bus contention in a multifunction integrated circuit under testing. The system is implemented in an integrated circuit adapted to accept a series of test inputs operable for testing the functionality of the integrated circuit. The integrated circuit includes at least one bus for communicatively coupling the multiple functional blocks. At least a first functional block and a second functional block included in the integrated circuit, the first functional block and the second functional block both coupled to the bus and coupled to accept the test inputs. An output enable controller is also included in the integrated circuit. The output enable controller is coupled to the second functional block and is operable to disable at least one output of the second functional block if a corresponding output of the first functional block is activated.

Abstract: A system for preventing bus contention in a multifunction integrated circuit during testing. The system is implemented in an integrated circuit adapted to accept a series of test inputs operable for testing the functionality of the integrated circuit. The integrated circuit includes at least one bus for communicatively coupling the multiple functional blocks. At least a first functional block and a second functional block included in the integrated circuit, the first functional block and the second functional block both coupled to the bus and coupled to accept the test inputs. A bus arbiter is also included in the integrated circuit for granting ownership of the bus. The bus arbiter is operable to disable at least one output of the second functional block if a corresponding output of the first functional block is activated by using a bus grant signal generated for the first functional block.

Abstract: A keyboard controller for a computer system with integrated Real Time Clock (RTC) functionality. The keyboard controller has a microprocessor for controlling peripheral device bus traffic such as keyboard and mouse traffic. The microprocessor also acts as a boot device for the computer system. By programming the microprocessor to emulate RTC functions, adding a divider circuit, and having an I/O support block which stores RTC registers and an extended CMOS RAM memory block, the entire RTC FSB along with its power detection and switching circuit can be removed.

Abstract: A system for clamping a clock signal line that prevents clock glitching is disclosed. The system is comprised of a plurality of logic gates which generates a signal to clamp the clock signal line only on the occurrence of the clock signal line being low, a clock clamping signal 26 is generated indicating that a peripheral device wants to clamp the clock signal line, and a start condition is detected indicating that the clock signal line may be clamped.