Patents by Inventor Brian M. Appold

Brian M. Appold has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6388470
    Abstract: The system and method facilitates the transmission of relatively high voltage signals via a thin oxide gate CMOS device without an excessively detrimental electric field build up across the thin oxide layers forming a gate in a CMOS device. The high voltage CMOS thin oxide gate system and method provides a degradation repression bias voltage signal to the thin oxide gate of the CMOS device. The degradation repression bias voltage signal establishes a differential voltage potential between the source and drain components of the thin oxide gate output CMOS device and the gate component of the thin oxide gate output CMOS device. The degradation repression bias voltage signal is maintained at a level that prevents that excessively detrimental electric field stresses are not induced in oxide layers that form the thin oxide gate in the output CMOS device.
    Type: Grant
    Filed: March 30, 2000
    Date of Patent: May 14, 2002
    Assignee: Philips Electronics North American Corporation
    Inventors: Derwin W. Mattos, Brian M. Appold
  • Patent number: 5481203
    Abstract: A test socket assembly includes a test and failure-analysis socket and an adapter board. Only the top interior surfaces of a QFP package mounted in the test socket are available for testing and probing. The socket must then be used for testing and analyzing only QFP integrated-circuit packages where the die is available for access from the top of the test socket. QFP integrated-circuit packages with a cavity-down configuration which were mounted upside-down in the test socket would have its lead connections to the test socket "scrambled" and would not match the input-pin pattern of the automatic test equipment. The adapter board to "unscramble" the connections between the tester and the test socket with a cavity-down QFP device, which is mounted upside down in the test socket, allowing the test socket to be used with a cavity-down device.
    Type: Grant
    Filed: August 5, 1994
    Date of Patent: January 2, 1996
    Assignee: VLSI Technology, Inc.
    Inventor: Brian M. Appold
  • Patent number: 5159266
    Abstract: A test socket and a method is provided for mounting and testing a quad flat pack QFP integrated-circuit package, where the QFP package has its leads cut to extend a predetermined distance from the sidewalls of the QFP integrated circuit package. The test socket includes a base to which are mounted a number of resilient contact blades having contacts for contacting the cut leads of the QFP device. A number of tester connection pins are mounted in the base and are connected to the contact blades. A movable comb member spaces the contact blades apart and is adjustably positioned to urge the contact blades into contact with the cut leads of a QFP device.
    Type: Grant
    Filed: July 31, 1991
    Date of Patent: October 27, 1992
    Assignee: VLSI Technology, Inc.
    Inventor: Brian M. Appold