Patents by Inventor Brian M. Dreibelbis
Brian M. Dreibelbis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10970448Abstract: Systems and methods for improving timing closure of new and existing IC chips by breaking at least one parameter of interest into two or more partial parameters. More specifically, a method is provided for that includes propagating at least one timing analysis run for a semiconductor product. The method further includes identifying at least one parameter of interest used in the at least one timing analysis run. The method further includes splitting the at least one parameter into two parts comprising a controlled part and an uncontrolled part. The method further includes correlating or anti-correlating the controlled part with another parameter used in the at least one timing analysis run. The method further includes projecting timing using the correlation or anti-correlation between the controlled part and the another parameter and using the uncontrolled part of the at least one parameter.Type: GrantFiled: July 18, 2019Date of Patent: April 6, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman, Jeffrey G. Hemmett, Lansing D. Pickup, Natesan Venkateswaran, Chandramouli Visweswariah, Vladimir Zolotov
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Patent number: 10489540Abstract: Solutions for integrating manufacturing feedback into an integrated circuit design are disclosed. In one embodiment, a computer-implemented method is disclosed including: defining an acceptable yield requirement for a first integrated circuit product; obtaining manufacturing data about the first integrated circuit product; performing a regression analysis on data representing paths in the first integrated circuit product to define a plurality of parameter settings based upon the acceptable yield requirement and the manufacturing data; determining a projection corner associated with the parameter settings for satisfying the acceptable yield requirement; and modifying a design of a second integrated circuit product based upon the projection corner and the plurality of parameter settings.Type: GrantFiled: November 13, 2017Date of Patent: November 26, 2019Assignee: International Business Machines CorporationInventors: Nathan C. Buck, Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman, Peter A. Habitz, Jeffrey G. Hemmett, Natesan Venkateswaran, Chandramouli Visweswariah, Xiaoyue Wang, Vladimir Zolotov
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Publication number: 20190340323Abstract: Systems and methods for improving timing closure of new and existing IC chips by breaking at least one parameter of interest into two or more partial parameters. More specifically, a method is provided for that includes propagating at least one timing analysis run for a semiconductor product. The method further includes identifying at least one parameter of interest used in the at least one timing analysis run. The method further includes splitting the at least one parameter into two parts comprising a controlled part and an uncontrolled part. The method further includes correlating or anti-correlating the controlled part with another parameter used in the at least one timing analysis run. The method further includes projecting timing using the correlation or anti-correlation between the controlled part and the another parameter and using the uncontrolled part of the at least one parameter.Type: ApplicationFiled: July 18, 2019Publication date: November 7, 2019Inventors: Brian M. DREIBELBIS, John P. DUBUQUE, Eric A. FOREMAN, Jeffrey G. HEMMETT, Lansing D. PICKUP, Natesan VENKATESWARAN, Chandramouli VISWESWARIAH, Vladimir ZOLOTOV
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Patent number: 10394982Abstract: Systems and methods for improving timing closure of new and existing IC chips by breaking at least one parameter of interest into two or more partial parameters. More specifically, a method is provided for that includes propagating at least one timing analysis run for a semiconductor product. The method further includes identifying at least one parameter of interest used in the at least one timing analysis run. The method further includes splitting the at least one parameter into two parts comprising a controlled part and an uncontrolled part. The method further includes correlating or anti-correlating the controlled part with another parameter used in the at least one timing analysis run. The method further includes projecting timing using the correlation or anti-correlation between the controlled part and the another parameter and using the uncontrolled part of the at least one parameter.Type: GrantFiled: February 26, 2014Date of Patent: August 27, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman, Jeffrey G. Hemmett, Lansing D. Pickup, Natesan Venkateswaran, Chandramouli Visweswariah, Vladimir Zolotov
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Publication number: 20180096089Abstract: Solutions for integrating manufacturing feedback into an integrated circuit design are disclosed. In one embodiment, a computer-implemented method is disclosed including: defining an acceptable yield requirement for a first integrated circuit product; obtaining manufacturing data about the first integrated circuit product; performing a regression analysis on data representing paths in the first integrated circuit product to define a plurality of parameter settings based upon the acceptable yield requirement and the manufacturing data; determining a projection corner associated with the parameter settings for satisfying the acceptable yield requirement; and modifying a design of a second integrated circuit product based upon the projection corner and the plurality of parameter settings.Type: ApplicationFiled: November 13, 2017Publication date: April 5, 2018Inventors: Nathan C. Buck, Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman, Peter A. Habitz, Jeffrey G. Hemmett, Natesan Venkateswaran, Chandramouli Visweswariah, Xiaoyue Wang, Vladimir Zolotov
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Patent number: 9858368Abstract: Solutions for integrating manufacturing feedback into an integrated circuit design are disclosed. In one embodiment, a computer-implemented method is disclosed including: defining an acceptable yield requirement for a first integrated circuit product; obtaining manufacturing data about the first integrated circuit product; performing a regression analysis on data representing paths in the first integrated circuit product to define a plurality of parameter settings based upon the acceptable yield requirement and the manufacturing data; determining a projection corner associated with the parameter settings for satisfying the acceptable yield requirement; and modifying a design of a second integrated circuit product based upon the projection corner and the plurality of parameter settings.Type: GrantFiled: July 13, 2011Date of Patent: January 2, 2018Assignee: International Business Machines CorporationInventors: Nathan C. Buck, Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman, Peter A. Habitz, Jeffrey G. Hemmett, Natesan Venkateswaran, Chandramouli Visweswariah, Xiaoyue Wang, Vladmimir Zolotov
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Publication number: 20160378903Abstract: Methods and systems receive an integrated circuit design into a computerized device and perform an analysis of the integrated circuit design to identify characteristics of physical features of portions of the integrated circuit design. Such methods and systems determine whether to look up sensitivity of a timing value of a portion of the integrated circuit design to manufacturing process variables, voltage variables, and temperature variables (PVT variables) by: evaluating relationships between the characteristics of physical features of the portion of the integrated circuit design to generate an indicator value; and, based on whether the indicator value is within a table usage filter value range, either: calculating the sensitivity of the timing value to the PVT variables; or looking up a previously determined sensitivity of the timing value to the PVT variables from a look-up table.Type: ApplicationFiled: June 26, 2015Publication date: December 29, 2016Inventors: Nathan Buck, Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman, David J. Hathaway, Jeffrey G. Hemmett, Kerim Kalafala, Gregory M. Schaeffer, Stephen G. Shuma, Natesan Venkateswaran, Chandramouli Visweswariah, Vladimir Zolotov
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Patent number: 9519747Abstract: Methods and systems receive an integrated circuit design into a computerized device and perform an analysis of the integrated circuit design to identify characteristics of physical features of portions of the integrated circuit design. Such methods and systems determine whether to look up sensitivity of a timing value of a portion of the integrated circuit design to manufacturing process variables, voltage variables, and temperature variables (PVT variables) by: evaluating relationships between the characteristics of physical features of the portion of the integrated circuit design to generate an indicator value; and, based on whether the indicator value is within a table usage filter value range, either: calculating the sensitivity of the timing value to the PVT variables; or looking up a previously determined sensitivity of the timing value to the PVT variables from a look-up table.Type: GrantFiled: June 26, 2015Date of Patent: December 13, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Nathan Buck, Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman, David J. Hathaway, Jeffrey G. Hemmett, Kerim Kalafala, Gregory M. Schaeffer, Stephen G. Shuma, Natesan Venkateswaran, Chandramouli Visweswariah, Vladimir Zolotov
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Publication number: 20150242554Abstract: Systems and methods for improving timing closure of new and existing IC chips by breaking at least one parameter of interest into two or more partial parameters. More specifically, a method is provided for that includes propagating at least one timing analysis run for a semiconductor product. The method further includes identifying at least one parameter of interest used in the at least one timing analysis run. The method further includes splitting the at least one parameter into two parts comprising a controlled part and an uncontrolled part. The method further includes correlating or anti-correlating the controlled part with another parameter used in the at least one timing analysis run. The method further includes projecting timing using the correlation or anti-correlation between the controlled part and the another parameter and using the uncontrolled part of the at least one parameter.Type: ApplicationFiled: February 26, 2014Publication date: August 27, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brian M. DREIBELBIS, John P. DUBUQUE, Eric A. FOREMAN, Jeffrey G. HEMMETT, Lansing D. PICKUP, Natesan VENKATESWARAN, Chandramouli VISWESWARIAH, Vladimir ZOLOTOV
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Patent number: 8768679Abstract: A computer-implemented method that simulates NPskew effects on a combination NFET (Negative Field Effect Transistor)/PFET (Positive Field Effect Transistor) semiconductor device using slew perturbations includes performing a timing test by a computing device, by: (1) evaluating perturb slews in Strong N/Weak P directions on the combination semiconductor device for a timing test result; (2) evaluation perturb slews in Weak N/Strong P directions on the combination semiconductor device for a timing test result; and (3) evaluating unperturbed slews in a balanced condition on the combination semiconductor device for a timing test result. After each test is performed, a determination is made as to which evaluation of the perturbed and unperturbed slews produces a most conservative timing test result for the combination semiconductor device. An NPskew effect adjusted timing test result is finally output based on determining the most conservative timing test result.Type: GrantFiled: September 30, 2010Date of Patent: July 1, 2014Assignee: International Business Machines CorporationInventors: Nathan C. Buck, Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman, Peter A. Habitz, Jeffrey G. Hemmett, Natesan Venkateswaran, Chandramouli Visweswariah, Xiaoyue X. Wang
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Patent number: 8656207Abstract: A method performs statistical static timing analysis of a network that includes a phase-locked loop and a feedback path. The feedback path comprises a set of delays operatively connected from the output of the phase-locked loop back to the input of the phase-locked loop. One embodiment herein computes a statistical feedback path delay for the feedback path. The method can use a separate statistical parameter to represent random uncorrelated delay variation for each delay in the feedback path. The method also computes an output arrival time for the phase-locked loop based on the negative of the statistical feedback path delay.Type: GrantFiled: December 15, 2009Date of Patent: February 18, 2014Assignee: International Business Machines CorporationInventors: Nathan C. Buck, Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman, Peter A. Habitz
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Patent number: 8468483Abstract: In embodiments of a statistical static timing analysis (SSTA) method, system and program storage device, the interdependence between the setup time and hold time margins of a circuit block (e.g., a latch, flip-flop, etc., which requires the checking of setup and hold timing constraints) is determined, taking into account possible variations in multiple parameters (e.g., using a variation-aware characterizing technique). A parameterized statistical static timing analysis (SSTA) of a circuit incorporating the circuit block is performed in order to determine, in statistical parameterized form, setup and hold times for the circuit block. Based on the interdependence between the setup and hold time margins, setup and hold time constraints can be determined in statistical parameterized form. Finally, the setup and hold times determined during the SSTA can be checked against the setup and hold time constraints to determine, if the time constraints are violated or not and to what degree.Type: GrantFiled: October 24, 2011Date of Patent: June 18, 2013Assignee: International Business Machines CorporationInventors: Nathan C. Buck, Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman, Peter A. Habitz, Jeffrey G. Hemmett, Natesan Venkateswaran, Chandramouli Visweswariah, Xiaoyue Wang, Vladimir Zolotov
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Publication number: 20130104092Abstract: In embodiments of a statistical static timing analysis (SSTA) method, system and program storage device, the interdependence between the setup time and hold time margins of a circuit block (e.g., a latch, flip-flop, etc., which requires the checking of setup and hold timing constraints) is determined, taking into account possible variations in multiple parameters (e.g., using a variation-aware characterizing technique). A parameterized statistical static timing analysis (SSTA) of a circuit incorporating the circuit block is performed in order to determine, in statistical parameterized form, setup and hold times for the circuit block. Based on the interdependence between the setup and hold time margins, setup and hold time constraints can be determined in statistical parameterized form. Finally, the setup and hold times determined during the SSTA can be checked against the setup and hold time constraints to determine, if the time constraints are violated or not and to what degree.Type: ApplicationFiled: October 24, 2011Publication date: April 25, 2013Applicant: International Business Machines CorporationInventors: Nathan C. Buck, Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman, Peter A. Habitz, Jeffrey G. Hemmett, Natesan Venkateswaran, Chandramouli Visweswariah, Xiaoyue Wang, Vladimir Zolotov
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Publication number: 20130018617Abstract: Solutions for integrating manufacturing feedback into an integrated circuit design are disclosed. In one embodiment, a computer-implemented method is disclosed including: defining an acceptable yield requirement for a first integrated circuit product; obtaining manufacturing data about the first integrated circuit product; performing a regression analysis on data representing paths in the first integrated circuit product to define a plurality of parameter settings based upon the acceptable yield requirement and the manufacturing data; determining a projection corner associated with the parameter settings for satisfying the acceptable yield requirement; and modifying a design of a second integrated circuit product based upon the projection corner and the plurality of parameter settings.Type: ApplicationFiled: July 13, 2011Publication date: January 17, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Nathan C. Buck, Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman, Peter A. Habitz, Jeffrey G. Hemmett, Natesan Venkateswaran, Chandramouli Visweswariah, Xiaoyue Wang, Vladmimir Zolotov
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Publication number: 20120084066Abstract: A computer-implemented method that simulates NPskew effects on a combination NFET (Negative Field Effect Transistor)/PFET (Positive Field Effect Transistor) semiconductor device using slew perturbations includes performing a timing test by a computing device, by: (1) evaluating perturb slews in Strong N/Weak P directions on the combination semiconductor device for a timing test result; (2) evaluation perturb slews in Weak N/Strong P directions on the combination semiconductor device for a timing test result; and (3) evaluating unperturbed slews in a balanced condition on the combination semiconductor device for a timing test result. After each test is performed, a determination is made as to which evaluation of the perturbed and unperturbed slews produces a most conservative timing test result for the combination semiconductor device. An NPskew effect adjusted timing test result is finally output based on determining the most conservative timing test result.Type: ApplicationFiled: September 30, 2010Publication date: April 5, 2012Applicant: International Business Machines CorporationInventors: Nathan C. Buck, Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman, Peter A. Habitz, Jeffrey G. Hemmett, Natesan Venkateswaran, Chandramouli Visweswariah, Xiaoyue X. Wang
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Patent number: 8141012Abstract: An approach for covering multiple selective timing corners in a single statistical timing run is described. In one embodiment, a single statistical timing analysis is run on the full parameter space that covers unlimited process parameters/environment conditions. Results from the statistical timing analysis are projected for selected corners. Timing closure is performed on the corners having the worst slacks.Type: GrantFiled: August 27, 2009Date of Patent: March 20, 2012Assignee: International Business Machines CorporationInventors: Nathan C. Buck, Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman, Peter A. Habitz, Jeffrey G. Hemmett, Susan K. Lichtensteiger, Natesan Venkateswaran, Chandramouli Visweswariah, Xiaoyue Wang
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Patent number: 8056035Abstract: A method of performing statistical timing analysis of a logic design, including effects of signal coupling, includes performing a deterministic analysis to determine deterministic coupling information for at least one aggressor/victim net pair of the logic design. Additionally, the method includes performing a statistical timing analysis in which the deterministic coupling information for the at least one aggressor/victim net pair is combined with statistical values of the statistical timing analysis to determine a statistical effective capacitance of a victim of the aggressor/victim net pair. Furthermore, the method includes using the statistical effective capacitance to determine timing data used in the statistical timing analysis.Type: GrantFiled: June 4, 2008Date of Patent: November 8, 2011Assignee: International Business Machines CorporationInventors: Nathan C. Buck, Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman, Peter A. Habitz, David J. Hathaway, Gregory M. Schaeffer, Chandramouli Visweswariah
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Publication number: 20110140745Abstract: A method performs statistical static timing analysis of a network that includes a phase-locked loop and a feedback path. The feedback path comprises a set of delays operatively connected from the output of the phase-locked loop back to the input of the phase-locked loop. One embodiment herein computes a statistical feedback path delay for the feedback path. The method can use a separate statistical parameter to represent random uncorrelated delay variation for each delay in the feedback path. The method also computes an output arrival time for the phase-locked loop based on the negative of the statistical feedback path delay.Type: ApplicationFiled: December 15, 2009Publication date: June 16, 2011Applicant: International Business Machines CorporatinoInventors: Nathan C. Buck, Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman, Peter A. Habitz
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Publication number: 20110055793Abstract: An approach for covering multiple selective timing corners in a single statistical timing run is described. In one embodiment, a single statistical timing analysis is run on the full parameter space that covers unlimited process parameters/environment conditions. Results from the statistical timing analysis are projected for selected corners. Timing closure is performed on the corners having the worst slacks.Type: ApplicationFiled: August 27, 2009Publication date: March 3, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Nathan C. Buck, Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman, Peter A. Habitz, Jeffrey G. Hemmett, Susan K. Lichtensteiger, Natesan Venkateswaran, Chandramouli Visweswariah, Xiaoyue Wang
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Publication number: 20090307645Abstract: A method of performing statistical timing analysis of a logic design, including effects of signal coupling, includes performing a deterministic analysis to determine deterministic coupling information for at least one aggressor/victim net pair of the logic design. Additionally, the method includes performing a statistical timing analysis in which the deterministic coupling information for the at least one aggressor/victim net pair is combined with statistical values of the statistical timing analysis to determine a statistical effective capacitance of a victim of the aggressor/victim net pair. Furthermore, the method includes using the statistical effective capacitance to determine timing data used in the statistical timing analysis.Type: ApplicationFiled: June 4, 2008Publication date: December 10, 2009Inventors: Nathan C. Buck, Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman, Peter A. Habitz, David J. Hathaway, Gregory M. Schaeffer, Chandramouli Visweswariah