Abstract: An integrated circuit (IC) device tester includes contact probes. A liner is formed upon the contact probes. The liner includes a matrix of metal particles and glass particles. The metal particles of the liner allow the contact probe to pass an electrical current through the liner. The glass particles of the liner prevent C4 material from adhering to the liner.

Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.

Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. An access instruction may be sent from the IC chip to the memory through a wiring line of the IC chip carrier. Power potential may be sent from a system board to the memory through a vertical interconnect access (VIA). Alternatively, an access instruction may be sent from a first IC chip to the memory and power potential may be sent from a second IC chip to the memory.

Abstract: A finned contact of an IC device may be utilized to electrically connect the IC device to external circuitry. The finned contact may be fabricated by forming a base upon the IC device and subsequently forming two or more fins upon the base. Each fin may be formed of the same and/or different material(s) as the base. Each fin may include layer(s) of one or materials. The fins may be located upon the base inset from the sidewall(s) of the base. The fins may be arranged as separated ring portions that are concentric with the base. The fins may drive current into the external circuitry connected thereto. Solder may be drawn towards the center of the base within an inner void that is internal to the fins, thereby limiting the likelihood of solder bridging with a neighboring contact.

Abstract: A finned contact of an IC device may be utilized to electrically connect the IC device to external circuitry. The finned contact may be fabricated by forming a base upon the IC device and subsequently forming two or more fins upon the base. Each fin may be formed of the same and/or different material(s) as the base. Each fin may include layer(s) of one or materials. The fins may be located upon the base inset from the sidewall(s) of the base. The fins may be arranged as separated ring portions that are concentric with the base. The fins may drive current into the external circuitry connected thereto. Solder may be drawn towards the center of the base within an inner void that is internal to the fins, thereby limiting the likelihood of solder bridging with a neighboring contact.

Abstract: An integrated circuit (IC) device tester includes contact probes. A liner is formed upon the contact probes. The liner includes a matrix of metal particles and glass particles. The metal particles of the liner allow the contact probe to pass an electrical current through the liner. The glass particles of the liner prevent C4 material from adhering to the liner.

Abstract: An integrated circuit (IC) device tester includes contact probes. A liner is formed upon the contact probes. The liner includes a matrix of an electrical conductor and glass. The conductor of the liner provides for the contact probe to be electrically connected to the IC device contact. The glass of the liner prevents IC device contact material adhering thereto. The liner may be formed by applying a conductive glass frit upon a probe card that includes the probe contacts and locally thermally conditioning the conductive glass frit upon contact probes. By locally thermally conditioning the conductive glass frit, the temperature of the probe card may be maintained below a critical temperature that damages the probe card.

Abstract: A module includes a laminate, the laminate including a solder mask layer and at least one depression in an upper surface of the solder mask layer that does not pass all of the way through the solder mask layer. The module also includes a first electronic element disposed in a first of the at least one depressions.

Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.

Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. An access instruction may be sent from the IC chip to the memory through a wiring line of the IC chip carrier. Power potential may be sent from a system board to the memory through a vertical interconnect access (VIA). Alternatively, an access instruction may be sent from a first IC chip to the memory and power potential may be sent from a second IC chip to the memory.

Abstract: An integrated circuit (IC) device tester includes contact probes. A liner is formed upon the contact probes. The liner includes a matrix of an electrical conductor and glass. The conductor of the liner provides for the contact probe to be electrically connected to the IC device contact. The glass of the liner prevents IC device contact material adhering thereto. The liner may be formed by applying a conductive glass frit upon a probe card that includes the probe contacts and locally thermally conditioning the conductive glass frit upon contact probes. By locally thermally conditioning the conductive glass frit, the temperature of the probe card may be maintained below a critical temperature that damages the probe card.

Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.

Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.

Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.

Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.

Abstract: A module includes a laminate, the laminate including a solder mask layer and at least one depression in an upper surface of the solder mask layer that does not pass all of the way through the solder mask layer. The module also includes a first electronic element disposed in a first of the at least one depressions.

Abstract: A module includes a laminate, the laminate including a solder mask layer and at least one depression in an upper surface of the solder mask layer that does not pass all of the way through the solder mask layer. The module also includes a first electronic element disposed in a first of the at least one depressions.

Abstract: A method of making a security mesh comprises forming on a conductive substrate an alumina film having through-holes in which metal, e.g., copper, through-wires are formed. First surface wires are formed on one surface of the alumina film and second surface wires are formed on the second, opposite surface of the alumina film in order to connect selected through-wires into a continuous undulating electrical circuit embedded within the alumina film. The security mesh product comprises an alumina film having a continuous undulating electrical circuit comprising copper or other conductive metal extending therethrough. A stacked security mesh comprises two or more of the mesh products being stacked one above the other.

Abstract: A semiconductor structure includes an electrically conductive structure formed upon an uppermost organic layer of a semiconductor substrate. A capping layer is formed upon the uppermost organic layer covering the electrically conductive structure. A maskless selective removal lasering technique ejects portions of the capping layer while retaining the portion of the capping layer covering the electrically conductive structure. Portions of the capping layer are ejected from the uppermost organic layer by a shockwave as a result of the laser beam vaporizing the uppermost organic layer of the semiconductor substrate. Portions of the capping layer contacting the electrically conductive structure are retained by the conductive structure dissipating heat from the laser that would otherwise vaporize the uppermost organic layer of the semiconductor substrate.

Abstract: A semiconductor structure includes an electrically conductive structure formed upon an uppermost organic layer of a semiconductor substrate. A capping layer is formed upon the uppermost organic layer covering the electrically conductive structure. A maskless selective removal lasering technique ejects portions of the capping layer while retaining the portion of the capping layer covering the electrically conductive structure. Portions of the capping layer are ejected from the uppermost organic layer by a shockwave as a result of the laser beam vaporizing the uppermost organic layer of the semiconductor substrate. Portions of the capping layer contacting the electrically conductive structure are retained by the conductive structure dissipating heat from the laser that would otherwise vaporize the uppermost organic layer of the semiconductor substrate.