Abstract: A system for compressed data transfer across a graphics bus in a computer system. The system includes a bridge, a system memory coupled to the bridge, and a graphics bus coupled to the bridge. A graphics processor is coupled to the graphics bus. The graphics processor is configured to compress graphics data and transfer compressed graphics data across the graphics bus to the bridge for subsequent storage in the system memory.

Abstract: An electronic device is assigned to a virtual bin by setting an operating voltage of the electronic device to a first voltage, determining an operating frequency and an operating power consumption level for the electronic device, determining an operating frequency differential equal to the absolute value of difference between the operating frequency and a minimum operating frequency of the physical bin, determining a power consumption level differential equal to the absolute value of difference between the operating power consumption level and a maximum operating power consumption level of the physical bin, and assigning a virtual bin identifier to the electronic device to identify the operating voltage of the electronic device if the operating frequency is greater than or equal to the minimum operating frequency of the physical bin and the operating power consumption level is less than or equal to the maximum power consumption level of the physical bin.

Abstract: Multiprocessor graphics systems support distributed antialiasing. In one embodiment, two (or more) graphics processors each render a version of the same image, with a difference in the sampling location (or locations) used for each pixel. A display head combines corresponding pixels generated by different graphics processors to produce an antialiased image. This distributed antialiasing technique can be scaled to any number of graphics processors.

Abstract: The present invention performance enhancement and reliability maintenance system and method pushes a processor to its maximized performance capabilities when performing processing intensive tasks (e.g., 3D graphics, etc). For example, a clock speed and voltage are increased until an unacceptable error rate begins to appear in the processing results and then the clock speed and voltage are backed off to the last setting at which excessive errors did not occur, enabling a processor at its full performance potential. The present invention also includes the ability to throttle back settings which facilitates the maintenance of desired reliability standards. The present invention is readily expandable to provide adjustment for a variety of characteristics in response to task performance requirements. For example, a variable speed fan that is software controlled can be adjusted to alter the temperature of the processor in addition to clock frequency and voltage.

Abstract: The present invention performance enhancement and reliability maintenance system and method pushes a processor to its maximized performance capabilities when performing processing intensive tasks (e.g., 3D graphics, etc). For example, a clock speed and voltage are increased until an unacceptable error rate begins to appear in the processing results and then the clock speed and voltage are backed off to the last setting at which excessive errors did not occur, enabling a processor at its full performance potential. The present invention also includes the ability to throttle back settings which facilitates the maintenance of desired reliability standards. The present invention is readily expandable to provide adjustment for a variety of characteristics in response to task performance requirements. For example, a variable speed fan that is software controlled can be adjusted to alter the temperature of the processor in addition to clock frequency and voltage.

Abstract: A system and method for optimizing power usage and performance during data processing. A multi-processor graphics processing system includes a low power graphics processor and a high performance graphics processor. When a low power condition exists only the low power graphics processor is used to process graphics data and the high performance graphics processor is turned off. When turned off, the high performance graphics processor does not consume either static or dynamic power. When the low power condition does not exist, the high performance graphics processor is turned on and the low power graphics processor and the high performance graphics processor are used to process the graphics data.

Abstract: One embodiment of a reconfigurable graphics processing system includes a first MXM edge connector and a second MXM edge connector affixed to an interposer board and a first MXM board and a second MXM board coupled to the interposer board via the first and second MXM edge connectors, respectively. Each MXM board includes a GPU and other elements necessary to process graphics data. The system couples to the motherboard of a computing device through an interface connector on the interposer board. One advantage of such a system is that it may be configured to deliver more performance than a standard desktop graphics board, while occupying substantially the same volume, through the use of multiple, small form factor MXM boards.

Abstract: A multi-chip graphics system includes a master chip and a slave chip coupled by an interlink. The slave chip performs pixel processing in parallel with the master chip, improving the performance of the master chip. In one embodiment, an individual graphics processing unit (GPU) chip includes a normal operational mode, a master mode, and a slave mode to permit an individual GPU chip to be used as individual processor or to be utilized as part of a master/slave pair.

Abstract: A multi-chip graphics system includes a master chip and a slave chip coupled by an interlink. The slave chip performs a graphics processing operation in parallel with the master chip, improving the performance of the master chip. In one embodiment, an individual graphics processing unit (GPU) chip includes a normal operational mode, a master mode, and a slave mode to permit an individual GPU chip to be used as individual processor or to be packaged as part of a master/slave pair.

Abstract: Multiprocessor graphics systems support distributed antialiasing. In one embodiment, two (or more) graphics processors each render a version of the same image, with a difference in the sampling location (or locations) used for each pixel. A display head combines corresponding pixels generated by different graphics processors to produce an antialiased image. This distributed antialiasing technique can be scaled to any number of graphics processors.

Abstract: A system and method processes graphics data for remote display. A graphics processing system including a plurality of graphics processing devices is coupled to a host system that includes a host graphics processor and a display device that is remote relative to the graphics processing system. Graphics processing performance may be scaled by distributing processing between the plurality of graphics processing devices and the host graphics processor such that each of the plurality of graphics processing devices and the host graphics processor produces a portion of an image. The portions are combined to produce the image, which is output by the host graphics processor to the display device.

Abstract: An integrated circuit includes an accelerated aging circuit block that has at least one circuit that ages at a faster rate than a functional circuit block. The accelerated aging circuit block is monitored during normal operation of the integrated circuit. Changes in the accelerated aging circuit block are used to generate data indicative of an aging trend for the functional circuit block.

Abstract: A scalable graphics processor architecture is disclosed in accordance with the present invention. In a first aspect, the architecture comprises a base graphics architecture. The architecture further includes an expansion graphic architecture, the expansion graphics architecture being mateably coupled to the base graphics architecture. In a second aspect, the architecture comprises a plurality of rendering processors, a first bus coupled to the plurality of processors for providing I/O signals to the processors; and a plurality of digital to analog converters (VDACs). In this aspect, each of the VDACs are adapted for driving a display. The architecture further includes a second bus coupled between the plurality of rendering processors and the plurality of VDACs for providing image data therebetween; and a switch, coupled to a plurality of processors.

Abstract: A system (30) draws antialiased polygons. A CPU (32) is connected to a floating point processor (FPU) (34) by bus (36). The CPU (32) is connected by a 32-bit system bus (38) to a random access memory (RAM) (40), a cache (42) and an interface (44) in graphics subsystem (45). The interface (44) is connected by bus (46) to graphics processor (48). The graphics processor (48) is connected by 120-bit graphics bus (50) to frame buffer (52). The frame buffer (52) is connected to a video digital to analog converter (DAC) (54) by bus (56). The DAC (54) is connected to video display (58) by line (60). The graphics processor (48) use a technique known as super-sampling to combat the effects of aliasing. In aliased mode, the graphics processor (48) use 16 array sites to sample 16 pixels (72). When drawing a polygon or line in antialiased mode, the graphics processor (48) uses the 16 sites to sample at 16 locations (120) within a single pixel (72).

Abstract: A system (30) for atomic access to an I/O device with DMA includes a CPU (32) connected to a floating point processor (FPU) (34) by bus (36). The CPU (32) is connected by a system bus (38) to a random access memory (RAM) (40), a cache (42) and an interface (44) in graphics subsystem (45). The interface (44) is connected by bus (46) to graphics processor (48). In this system, graphics subsystem (45) is an I/O device, and atomic access to it is required. Command packet interface (44) to the graphics subsystem (45) transfers geometry and graphics context information from main memory (40) to the graphics subsystem (45). For such transfers, an application writes a list of commands to a physically contiguous locked-down memory buffer (47) in its own address space. Since the system (30) has DMA, the buffer (47) resides in the main memory system (40).

Abstract: A method is provided for generating pixel color information for use in producing an image of a line segment on a graphics display screen, the method comprising the steps of: denoting at least one planar region of the display screen that encompasses the line segment; assigning respective intensity values for at least three selected pixels encompassed by the at least one planar region; assigning respective color values for the at least three selected pixels; and interpolating respective final color values for each respective pixel encompassed by the at least one planar region based upon the respective assigned intensity values and the respective assigned color values.

Abstract: A method is provided for generating pixel color information for use in producing an image of a line segment on a graphics display screen, the method comprising the steps of: denoting at least one planar region of the display screen that encompasses the line segment; assigning respective intensity values for at least three selected pixels encompassed by the at least one planar region; assigning respective color values for the at least three selected pixels; and interpolating respective final color values for each respective pixel encompassed by the at least one planar region based upon the respective assigned intensity values and the respective assigned color values.