Patents by Inventor Brian Maertz

Brian Maertz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11404630
    Abstract: A material layer stack for a pSTTM memory device includes a magnetic tunnel junction (MTJ) stack, a oxide layer, a protective layer and a capping layer. The MTJ includes a fixed magnetic layer, a tunnel barrier disposed above the fixed magnetic layer and a free magnetic layer disposed on the tunnel barrier. The oxide layer, which enables an increase in perpendicularity of the pSTTM material layer stack, is disposed on the free magnetic layer. The protective layer is disposed on the oxide layer, and acts as a protective barrier to the oxide from physical sputter damage during subsequent layer deposition. A conductive capping layer with a low oxygen affinity is disposed on the protective layer to reduce iron-oxygen de-hybridization at the interface between the free magnetic layer and the oxide layer. The inherent non-oxygen scavenging nature of the conductive capping layer enhances stability and reduces retention loss in pSTTM devices.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: August 2, 2022
    Assignee: Intel Corporation
    Inventors: Md Tofizur Rahman, Christopher J. Wiegand, Kaan Oguz, Justin S. Brockman, Daniel G. Ouellette, Brian Maertz, Kevin P. O'Brien, Mark L. Doczy, Brian S. Doyle, Oleg Golonzka, Tahir Ghani
  • Patent number: 11031545
    Abstract: Systems, apparatus, and methods for magnetoresitive memory are described. An apparatus for magnetoresitive memory includes a fixed layer, a free layer, and a tunneling barrier between the fixed layer and the free layer. The free layer is a new alloy consisting of a composition of Cobalt (Co), Iron (Fe), and Boron (B) intermixed with a non-magnetic metal according to a ratio. A thin insert layer of CoFeB may optionally be added between the alloy and the tunneling barrier.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Kaan Oguz, Kevin P. O'Brien, Brian S. Doyle, Mark L. Doczy, Charles C. Kuo, Daniel G. Ouellette, Christopher J. Wiegand, Md Tofizur Rahman, Brian Maertz
  • Patent number: 10868233
    Abstract: Strain engineering of perpendicular magnetic tunnel junctions (PMTJs) is described. In an example, a memory structure includes a perpendicular magnetic tunnel junction (pMTJ) element disposed above a substrate. A lateral strain-inducing material layer is disposed on the pMTJ element. An inter-layer dielectric (ILD) layer disposed laterally adjacent to both the pMTJ element and the lateral strain-inducing material layer.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: December 15, 2020
    Assignee: Intel Corporation
    Inventors: Daniel G. Ouellette, Christopher J. Wiegand, Md Tofizur Rahman, Brian Maertz, Oleg Golonzka, Justin S. Brockman, Kevin P. O'Brien, Brian S. Doyle, Kaan Oguz, Tahir Ghani, Mark L. Doczy
  • Patent number: 10804460
    Abstract: Material layer stack structures to provide a magnetic tunnel junction (MTJ) having improved perpendicular magnetic anisotropy (PMA) characteristics. In an embodiment, a free magnetic layer of the material layer stack is disposed between a tunnel barrier layer and a cap layer of magnesium oxide (Mg). The free magnetic layer includes a Cobalt-Iron-Boron (CoFeB) body substantially comprised of a combination of Cobalt atoms, Iron atoms and Boron atoms. A first Boron mass fraction of the CoFeB body is equal to or more than 25% (e.g., equal to or more than 27%) in a first region which adjoins an interface of the free magnetic layer with the tunnel barrier layer. In another embodiment, the first Boron mass fraction is more than a second Boron mass fraction in a second region of the CoFeB body which adjoins an interface of the free magnetic layer with the cap layer.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: October 13, 2020
    Assignee: Intel Corporation
    Inventors: MD Tofizur Rahman, Christopher J. Wiegand, Brian Maertz, Daniel G. Ouellette, Kevin P. O'Brien, Kaan Oguz, Brian S. Doyle, Mark L. Doczy, Daniel B. Bergstrom, Justin S. Brockman, Oleg Golonzka, Tahir Ghani
  • Patent number: 10770651
    Abstract: A material layer stack for a pSTTM device includes a fixed magnetic layer, a tunnel barrier disposed above the fixed magnetic layer and a free layer disposed on the tunnel barrier. The free layer further includes a stack of bilayers where an uppermost bilayer is capped by a magnetic layer including iron and where each of the bilayers in the free layer includes a non-magnetic layer such as Tungsten, Molybdenum disposed on the magnetic layer. In an embodiment, the non-magnetic layers have a combined thickness that is less than 15% of a combined thickness of the magnetic layers in the stack of bilayers. A stack of bilayers including non-magnetic layers in the free layer can reduce the saturation magnetization of the material layer stack for the pSTTM device and subsequently increase the perpendicular magnetic anisotropy.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: September 8, 2020
    Assignee: Intel Corporation
    Inventors: MD Tofizur Rahman, Christopher J. Wiegand, Kaan Oguz, Daniel G. Ouellette, Brian Maertz, Kevin P. O'Brien, Mark L. Doczy, Brian S. Doyle, Oleg Golonzka, Tahir Ghani
  • Patent number: 10636960
    Abstract: MTJ material stacks with a laterally strained free magnetic layer, STTM devices employing such stacks, and computing platforms employing such STTM devices. In some embodiments, perpendicular pMTJ material stacks included free magnetic layers that are compressively strained laterally by a surrounding material, which increases coercive field strength for a more stable device. In some embodiments, a pMTJ material stack is encased in a compressive-stressed material. In some further embodiments, a pMTJ material stack is encased first in a dielectric shell, permitting a conductive material to be deposited over the shell as the compressive-stressed, strain-inducing material layer.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: April 28, 2020
    Assignee: Intel Corporation
    Inventors: Prashanth P. Madras, MD Tofizur Rahman, Christopher J. Wiegand, Brian Maertz, Oleg Golonzka, Kevin P. O'Brien, Mark L. Doczy, Brian S. Doyle, Tahir Ghani, Kaan Oguz
  • Patent number: 10559744
    Abstract: An apparatus including an array of memory cells arranged in a grid defined by word lines and bit lines in a generally orthogonal orientation relative to one another, a memory cell including a resistive memory component and an access transistor, wherein the access transistor includes a diffusion region disposed at an acute angle relative to an associated word line. A method including etching a substrate to form a plurality of fins each including a body having a length dimension including a plurality of first junction regions and a plurality of second junction regions that are generally parallel to one another and offset by angled channel regions displacing in the length dimension an end of a first junction region from the beginning of a second junction region; removing the spacer material; and introducing a gate electrode on the channel region of each of the plurality of fins.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: February 11, 2020
    Assignee: Intel Corporation
    Inventors: Brian Maertz, Christopher J. Wiegand, Daniel G. Oeullette, Md Tofizur Rahman, Oleg Golonzka, Justin S. Brockman, Tahir Ghani, Brian S. Doyle, Kevin P. O'Brien, Mark L. Doczy, Kaan Oguz
  • Publication number: 20190378972
    Abstract: A material layer stack for a pSTTM device includes a fixed magnetic layer, a tunnel barrier disposed above the fixed magnetic layer and a free layer disposed on the tunnel barrier. The free layer further includes a stack of bilayers where an uppermost bilayer is capped by a magnetic layer including iron and where each of the bilayers in the free layer includes a non-magnetic layer such as Tungsten, Molybdenum disposed on the magnetic layer. In an embodiment, the non-magnetic layers have a combined thickness that is less than 15% of a combined thickness of the magnetic layers in the stack of bi-layers. A stack of bilayers including non-magnetic layers in the free layer can reduce the saturation magnetization of the material layer stack for the pSTTM device and subsequently increase the perpendicular magnetic anisotropy.
    Type: Application
    Filed: December 30, 2016
    Publication date: December 12, 2019
    Inventors: MD Tofizur RAHMAN, Christopher J. WIEGAND, Kaan OGUZ, Daniel G. OUELLETTE, Brian MAERTZ, Kevin P. O'BRIEN, Mark L. DOCZY, Brian S. DOYLE, Oleg GOLONZKA, Tahir GHANI
  • Publication number: 20190334079
    Abstract: A material layer stack for a pSTTM memory device includes a magnetic tunnel junction (MTJ) stack, a oxide layer, a protective layer and a capping layer. The MTJ includes a fixed magnetic layer, a tunnel barrier disposed above the fixed magnetic layer and a free magnetic layer disposed on the tunnel barrier. The oxide layer, which enables an increase in perpendicularity of the pSTTM material layer stack, is disposed on the free magnetic layer. The protective layer is disposed on the oxide layer, and acts as a protective barrier to the oxide from physical sputter damage during subsequent layer deposition. A conductive capping layer with a low oxygen affinity is disposed on the protective layer to reduce iron-oxygen de-hybridization at the interface between the free magnetic layer and the oxide layer. The inherent non-oxygen scavenging nature of the conductive capping layer enhances stability and reduces retention loss in pSTTM devices.
    Type: Application
    Filed: December 30, 2016
    Publication date: October 31, 2019
    Inventors: MD Tofizur RAHMAN, Christopher J. WIEGAND, Kaan OGUZ, Justin S. BROCKMAN, Daniel G. OUELLETTE, Brian MAERTZ, Kevin P. O'BRIEN, Mark L. DOCZY, Brian S. DOYLE, Oleg GOLONZKA, Tahir GHANI
  • Publication number: 20190221734
    Abstract: Systems, apparatus, and methods for magnetoresitive memory are described. An apparatus for magnetoresitive memory includes a fixed layer, a free layer, and a tunneling barrier between the fixed layer and the free layer. The free layer is a new alloy consisting of a composition of Cobalt (Co), Iron (Fe), and Boron (B) intermixed with a non-magnetic metal according to a ratio. A thin insert layer of CoFeB may optionally be added between the alloy and the tunneling barrier.
    Type: Application
    Filed: September 30, 2016
    Publication date: July 18, 2019
    Applicant: INTEL CORPORATION
    Inventors: Kaan Oguz, Kevin P. O'Brien, Brian S. Doyle, Mark L. Doczy, Charles C. Kuo, Daniel G. Ouellette, Christopher J. Wiegand, MD Tofizur Rahman, Brian Maertz
  • Publication number: 20190140166
    Abstract: Material layer stack structures to provide a magnetic tunnel junction (MTJ) having improved perpendicular magnetic anisotropy (PMA) characteristics. In an embodiment, a free magnetic layer of the material layer stack is disposed between a tunnel barrier layer and a cap layer of magnesium oxide (Mg). The free magnetic layer includes a Cobalt-Iron-Boron (CoFeB) body substantially comprised of a combination of Cobalt atoms, Iron atoms and Boron atoms. A first Boron mass fraction of the CoFeB body is equal to or more than 25% (e.g., equal to or more than 27%) in a first region which adjoins an interface of the free magnetic layer with the tunnel barrier layer. In another embodiment, the first Boron mass fraction is more than a second Boron mass fraction in a second region of the CoFeB body which adjoins an interface of the free magnetic layer with the cap layer.
    Type: Application
    Filed: July 1, 2016
    Publication date: May 9, 2019
    Inventors: MD Tofizur RAHMAN, Christopher J. WIEGAND, Brian MAERTZ, Daniel G. OUELLETTE, Kevin P. O'BRIEN, Kaan OGUZ, Brian S. DOYLE, Mark L. DOCZY, Daniel B. BERGSTROM, Justin S. BROCKMAN, Oleg GOLONZKA, Tahir GHANI
  • Publication number: 20190036010
    Abstract: An apparatus including an array of memory cells arranged in a grid defined by word lines and bit lines in a generally orthogonal orientation relative to one another, a memory cell including a resistive memory component and an access transistor, wherein the access transistor includes a diffusion region disposed at an acute angle relative to an associated word line. A method including etching a substrate to form a plurality of fins each including a body having a length dimension including a plurality of first junction regions and a plurality of second junction regions that are generally parallel to one another and offset by angled channel regions displacing in the length dimension an end of a first junction region from the beginning of a second junction region; removing the spacer material; and introducing a gate electrode on the channel region of each of the plurality of fins.
    Type: Application
    Filed: April 1, 2016
    Publication date: January 31, 2019
    Inventors: Brian MAERTZ, Christopher J. WIEGAND, Daniel G. OEULLETTE, MD Tofizur RAHMAN, Oleg GOLONZKA, Justin S. BROCKMAN, Tahir GHANI, Brian S. DOYLE, Kevin P. O'BRIEN, Mark L. DOCZY, Kaan OGUZ
  • Publication number: 20190027679
    Abstract: Approaches for strain engineering of perpendicular magnetic tunnel junctions (pMTJs), and the resulting structures, are described. In an example, a memory structure includes a perpendicular magnetic tunnel junction (pMTJ) element disposed above a substrate. A lateral strain-inducing material layer is disposed on the pMTJ element. An inter-layer dielectric (ILD) layer is disposed laterally adjacent to both the pMTJ element and the lateral strain-inducing material layer. The ILD layer has an uppermost surface co-planar or substantially co-planar with an uppermost surface of the lateral strain-inducing material layer.
    Type: Application
    Filed: March 30, 2016
    Publication date: January 24, 2019
    Applicant: Intel Corporation
    Inventors: Daniel G. OUELLETTE, Christopher J. WIEGAND, MD Tofizur RAHMAN, Brian MAERTZ, Oleg GOLONZKA, Justin S. BROCKMAN, Kevin P. O'BRIEN, Brian S. DOYLE, Kaan OGUZ, Tahir GHANI, Mark L. DOCZY
  • Publication number: 20180287050
    Abstract: MTJ material stacks with a laterally strained free magnetic layer, STTM devices employing such stacks, and computing platforms employing such STTM devices. In some embodiments, perpendicular pMTJ material stacks included free magnetic layers that are compressively strained laterally by a surrounding material, which increases coercive field strength for a more stable device. In some embodiments, a pMTJ material stack is encased in a compressive-stressed material. In some further embodiments, a pMTJ material stack is encased first in a dielectric shell, permitting a conductive material to be deposited over the shell as the compressive-stressed, strain-inducing material layer.
    Type: Application
    Filed: September 25, 2015
    Publication date: October 4, 2018
    Applicant: Intel Corporation
    Inventors: Prashanth P. Madras, MD Tofizur Rahman, Christopher J. Wiegand, Brian Maertz, Oleg Golonzka, Kevin P. O'Brien, Mark L. Doczy, Brian S. Doyle, Tahir Ghani, Kaan Oguz