Abstract: An adder circuit uses a summing circuit to provide a summed sliced bit number from a first sliced bit number and a second sliced bit number. A boundary circuit is operably connected to the summing circuit to form a rounding boundary between selected groups of the summed sliced bit number. A rounding circuit is operably connected to the boundary circuit to detect a zero in each slice of the summed sliced bit number while the first and second sliced bit numbers are being added to one another. The rounding circuit includes a logic circuit to detect the zero and provide a zero detect output and a control circuit to selectively round the summed sliced bit number up and down in response to the zero detect output.