Patents by Inventor Brian Matthew Henderson
Brian Matthew Henderson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9379201Abstract: A method includes thinning a back-side of a substrate to expose a portion of a first via that is formed in the substrate. The method also includes forming a first diode at the back-side of the substrate. The first diode is coupled to the first via.Type: GrantFiled: July 22, 2015Date of Patent: June 28, 2016Assignee: Qualcomm IncorporatedInventors: Vidhya Ramachandran, Brian Matthew Henderson, Shiqun Gu, Chiew-Guan Tan, Jung Pill Kim, Taehyun Kim
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Publication number: 20150333053Abstract: A method includes thinning a back-side of a substrate to expose a portion of a first via that is formed in the substrate. The method also includes forming a first diode at the back-side of the substrate. The first diode is coupled to the first via.Type: ApplicationFiled: July 22, 2015Publication date: November 19, 2015Inventors: Vidhya Ramachandran, Brian Matthew Henderson, Shiqun Gu, Chiew-Guan Tan, Jung Pill Kim, Taehyun Kim
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Patent number: 9190201Abstract: An integrated magnetic film enhanced inductor and a method of forming an integrated magnetic film enhanced inductor are disclosed. The integrated magnetic film enhanced inductor includes an inductor metal having a first portion and a second portion, a top metal or bottom metal coupled to the inductor metal, and an isolation film disposed one of in, on, and adjacent to at least one of the first portion and the second portion of the inductor metal. The isolation film includes a magnetic material, such as a magnetic film.Type: GrantFiled: March 4, 2009Date of Patent: November 17, 2015Assignee: QUALCOMM IncorporatedInventors: Xia Li, Matthew Nowak, Seung H. Kang, Brian Matthew Henderson
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Publication number: 20150048497Abstract: A photovoltaic (PV) substrate includes a grooved die-facing surface to form a channel for a bypass diode. The die-facing surface supports a screen-printed metal interconnect layer to form a first terminal for the bypass diode.Type: ApplicationFiled: August 16, 2013Publication date: February 19, 2015Applicant: QUALCOMM IncorporatedInventors: Brian Matthew Henderson, Shiqun Gu, Urmi Ray
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Patent number: 8912043Abstract: A stacked integrated circuit (IC) may be manufactured with a second tier wafer bonded to a double-sided first tier wafer. The double-sided first tier wafer includes back-end-of-line (BEOL) layers on a front and a back side of the wafer. Extended contacts within the first tier wafer connect the front side and the back side BEOL layers. The extended contact extends through a junction of the first tier wafer. The second tier wafer couples to the front side of the first tier wafer through the extended contacts. Additional contacts couple devices within the first tier wafer to the front side BEOL layers. When double-sided wafers are used in stacked ICs, the height of the stacked ICs may be reduced. The stacked ICs may include wafers of identical functions or wafers of different functions.Type: GrantFiled: July 18, 2013Date of Patent: December 16, 2014Assignee: QUALCOMM IncorporatedInventors: Arvind Chandrasekaran, Brian Matthew Henderson
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Publication number: 20140306349Abstract: Some implementations provide an interposer that includes a substrate, a via in the substrate, and an oxidation layer. The via includes a metal material. The oxidation layer is between the via and the substrate. In some implementations, the substrate is a silicon substrate. In some implementations, the oxidation layer is a thermal oxide formed by exposing the substrate to heat. In some implementations, the oxidation layer is configured to provide electrical insulation between the via and the substrate. In some implementations, the interposer also includes an insulation layer. In some implementations, the insulation layer is a polymer layer. In some implementations, the interposer also includes at least one interconnect on the surface of the interposer. The at least one interconnect is positioned on the surface of the interposer such that the oxidation layer is between the interconnect and the substrate.Type: ApplicationFiled: April 11, 2013Publication date: October 16, 2014Applicant: QUALCOMM IncorporatedInventors: Shiqun Gu, Urmi Ray, Roawen Chen, Brian Matthew Henderson, Ratibor Radojcic, Matthew Nowak, Nicholas Yu
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Publication number: 20140225246Abstract: Some implementations provide an integrated device that includes a first substrate, a first die coupled to the first substrate, a second die coupled to the first die, and a second substrate coupled to the second die. The second substrate is configured to provide an electrical path for a signal to the second die. The integrated device further includes a molding surrounding the first die and the second die, and several through mold vias (TMVs) coupled to the second substrate. The TMVs are configured to provide an electrical path for the signal to the second die through the second substrate. In some implementations, the second substrate includes a signal distribution structure configured to provide the electrical path for the signal to the second die. In some implementations, the first substrate and the second substrate are part of a signal distribution network that provides signal to the second die.Type: ApplicationFiled: December 18, 2013Publication date: August 14, 2014Applicant: QUALCOMM INCORPORATEDInventors: Brian Matthew Henderson, Durodami Joscelyn Lisk, Shiqun Gu, Ratibor Radojcic, Matthew Michael Nowak
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Patent number: 8618539Abstract: An interconnect sensor for detecting delamination due to coefficient of thermal expansion mismatch and/or mechanical stress. The sensor comprises a conductive path that includes a via disposed between two back end of line metal layers separated by a dielectric. The via is coupled between a first probe structure and a second probe structure and mechanically coupled to a stress inducing structure. The via is configured to alter the conductive path in response to mechanical stress caused by the stress inducing structure. The stress inducing structure can be a through silicon via or a solder ball. The dielectric material can be a low-k dielectric material. In another embodiment, a method of forming an interconnect sensor is provided for detecting delamination.Type: GrantFiled: November 5, 2009Date of Patent: December 31, 2013Assignee: QUALCOMM IncorporatedInventors: Brian Matthew Henderson, Shiqun Gu, Homyar C. Mogul, Mark M. Nakamoto, Arvind Chandrasekaran
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Publication number: 20130302943Abstract: A stacked integrated circuit (IC) may be manufactured with a second tier wafer bonded to a double-sided first tier wafer. The double-sided first tier wafer includes back-end-of-line (BEOL) layers on a front and a back side of the wafer. Extended contacts within the first tier wafer connect the front side and the back side BEOL layers. The extended contact extends through a junction of the first tier wafer. The second tier wafer couples to the front side of the first tier wafer through the extended contacts. Additional contacts couple devices within the first tier wafer to the front side BEOL layers. When double-sided wafers are used in stacked ICs, the height of the stacked ICs may be reduced. The stacked ICs may include wafers of identical functions or wafers of different functions.Type: ApplicationFiled: July 18, 2013Publication date: November 14, 2013Inventors: Arvind Chandrasekaran, Brian Matthew Henderson
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Patent number: 8536893Abstract: A circuit for recording a magnitude of an ESD event during semiconductor assembly includes a voltage divider connected between an input and a ground. The circuit also includes a measurement block having a recorder device. Each measurement block receives current from a segment of the voltage divider. The magnitude of the ESD event is determined based upon a read-out of the measurement devices after the ESD event. The recorder device may be a capacitor that would be damaged during the ESD event. During the ESD event the capacitor may be damaged. Reading out the recorder device determines if the magnitude of the ESD event exceeded a threshold magnitude that damages the capacitor.Type: GrantFiled: October 13, 2009Date of Patent: September 17, 2013Assignee: QUALCOMM IncorporatedInventors: Eugene R. Worley, Brian Matthew Henderson
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Patent number: 8508301Abstract: A three dimensional on-chip radio frequency amplifier is disclosed that includes first and second transformers and a first transistor. The first transformer includes first and second inductively coupled inductors. The second transformer includes third and fourth inductively coupled inductors. Each inductor includes multiple first segments in a first metal layer; multiple second segments in a second metal layer; first and second inputs, and multiple through vias coupling the first and second segments to form a continuous path between the first and second inputs. The first input of the first inductor is coupled to an amplifier input; the first input of the second inductor is coupled to the first transistor gate; the first input of the third inductor is coupled to the first transistor drain, the first input of the fourth inductor is coupled to an amplifier output. The second inductor inputs and the first transistor source are coupled to ground.Type: GrantFiled: November 11, 2011Date of Patent: August 13, 2013Assignee: QUALCOMM IncorporatedInventors: Jonghae Kim, Shiqun Gu, Brian Matthew Henderson, Thomas R. Toms, Lew G. Chua-Eoan, Seyfollah S. Bazarjani, Matthew Nowak
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Patent number: 8354300Abstract: Mitigating electrostatic discharge damage when fabricating a 3-D integrated circuit package, wherein in one embodiment when a second tier die is placed in contact with a first tier die, conductive bumps near the perimeter of the second tier die that are electrically coupled to the substrate of the second tier die make contact with corresponding conductive bumps on the first tier die that are electrically coupled to the substrate of first tier die before other signal conductive bumps and power conductive bumps on the second tier and first tier dice make electrical contact.Type: GrantFiled: February 23, 2010Date of Patent: January 15, 2013Assignee: QUALCOMM IncorporatedInventors: Brian Matthew Henderson, Arvind Chandrasekaran
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Patent number: 8350358Abstract: A semiconductor die includes a semiconductive substrate layer with first and second sides, a metal layer adjacent the second side of the semiconductive substrate layer, one or more active devices in an active layer on the first side of the semiconductive substrate layer; and a passive device in the metal layer in electrical communication with the active layer. The passive device can electrically couple to the active layer with through silicon vias (TSVs).Type: GrantFiled: September 13, 2011Date of Patent: January 8, 2013Assignee: QUALCOMM IncorporatedInventors: Jonghae Kim, Shiqun Gu, Brian Matthew Henderson, Thomas R. Toms, Matthew Nowak
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Patent number: 8324066Abstract: A method for manufacturing a semiconductor device includes fabricating an active layer on a first side of a semiconductor substrate. The method also includes fabricating a metal layer on a second side of the semiconductor substrate. The metal layer includes a passive device embedded within the metal layer. The passive device can electrically couple to the active layer with through vias.Type: GrantFiled: October 24, 2011Date of Patent: December 4, 2012Assignee: QUALCOMM IncorporatedInventors: Jonghae Kim, Shiqun Gu, Brian Matthew Henderson, Thomas R. Toms, Matthew Nowak
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Patent number: 8143952Abstract: A three dimensional on-chip inductor, transformer and radio frequency amplifier are disclosed. The radio frequency amplifier includes a pair of transformers and a transistor. The transformers include at least two inductively coupled inductors. The inductors include a plurality of segments of a first metal layer, a plurality of segments of a second metal layer, a first inductor input, a second inductor input, and a plurality of through silicon vias coupling the plurality of segments of the first metal layer and the plurality of segments of the second metal layer to form a continuous, non-intersecting path between the first inductor input and the second inductor input. The inductors can have a symmetric or asymmetric geometry. The first metal layer can be a metal layer in the back-end-of-line section of the chip. The second metal layer can be located in the redistributed design layer of the chip.Type: GrantFiled: October 8, 2009Date of Patent: March 27, 2012Assignee: QUALCOMM IncorporatedInventors: Jonghae Kim, Shiqun Gu, Brian Matthew Henderson, Thomas R. Toms, Lew G. Chua-Eoan, Seyfollah S. Bazarjani, Matthew Nowak
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Publication number: 20120056680Abstract: A three dimensional on-chip radio frequency amplifier is disclosed that includes first and second transformers and a first transistor. The first transformer includes first and second inductively coupled inductors. The second transformer includes third and fourth inductively coupled inductors. Each inductor includes multiple first segments in a first metal layer; multiple second segments in a second metal layer; first and second inputs, and multiple through vias coupling the first and second segments to form a continuous path between the first and second inputs. The first input of the first inductor is coupled to an amplifier input; the first input of the second inductor is coupled to the first transistor gate; the first input of the third inductor is coupled to the first transistor drain, the first input of the fourth inductor is coupled to an amplifier output. The second inductor inputs and the first transistor source are coupled to ground.Type: ApplicationFiled: November 11, 2011Publication date: March 8, 2012Applicant: QUALCOMM INCORPORATEDInventors: Jonghae Kim, Shiqun Gu, Brian Matthew Henderson, Thomas R. Toms, Lew G. Chua-Eoan, Seyfollah S. Bazarjani, Matthew Nowak
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Publication number: 20120040509Abstract: A method for manufacturing a semiconductor device includes fabricating an active layer on a first side of a semiconductor substrate. The method also includes fabricating a metal layer on a second side of the semiconductor substrate. The metal layer includes a passive device embedded within the metal layer. The passive device can electrically couple to the active layer with through vias.Type: ApplicationFiled: October 24, 2011Publication date: February 16, 2012Applicant: QUALCOMM INCORPORATEDInventors: Jonghae Kim, Shiqun Gu, Brian Matthew Henderson, Thomas R. Toms, Matthew Nowak
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Publication number: 20120001297Abstract: A semiconductor die includes a semiconductive substrate layer with first and second sides, a metal layer adjacent the second side of the semiconductive substrate layer, one or more active devices in an active layer on the first side of the semiconductive substrate layer; and a passive device in the metal layer in electrical communication with the active layer. The passive device can electrically couple to the active layer with through silicon vias (TSVs).Type: ApplicationFiled: September 13, 2011Publication date: January 5, 2012Applicant: QUALCOMM INCORPORATEDInventors: Jonghae Kim, Shiqun Gu, Brian Matthew Henderson, Thomas R. Toms, Matthew Nowak
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Patent number: 8067816Abstract: A semiconductor die includes a semiconductive substrate layer with first and second sides, a metal layer adjacent the second side of the semiconductive substrate layer, one or more active devices in an active layer on the first side of the semiconductive substrate layer; and a passive device in the metal layer in electrical communication with the active layer. The passive device can electrically couple to the active layer with through silicon vias (TSVs).Type: GrantFiled: February 3, 2009Date of Patent: November 29, 2011Assignee: QUALCOMM IncorporatedInventors: Jonghae Kim, Shiqun Gu, Brian Matthew Henderson, Thomas R. Toms, Matthew Nowak
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Publication number: 20110204504Abstract: Mitigating electrostatic discharge damage when fabricating a 3-D integrated circuit package, wherein in one embodiment when a second tier die is placed in contact with a first tier die, conductive bumps near the perimeter of the second tier die that are electrically coupled to the substrate of the second tier die make contact with corresponding conductive bumps on the first tier die that are electrically coupled to the substrate of first tier die before other signal conductive bumps and power conductive bumps on the second tier and first tier dice make electrical contact.Type: ApplicationFiled: February 23, 2010Publication date: August 25, 2011Applicant: QUALCOMM INCORPORATEDInventors: Brian Matthew Henderson, Arvind Chandrasekaran