Patents by Inventor Brian Messenger

Brian Messenger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8836003
    Abstract: Deep trench capacitor structures and methods of manufacture are disclosed. The method includes forming a deep trench structure in a wafer including a substrate, buried oxide layer (BOX) and silicon (SOI) film. The structure includes a wafer including a substrate, buried insulator layer and a layer of silicon on insulator layer (SOI) having a single crystalline structure throughout the layer. The structure further includes a first plate in the substrate and an insulator layer in direct contact with the first plate. A doped polysilicon is in direct contact with the insulator layer and also in direct contact with the single crystalline structure of the SOI.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Joseph Ervin, Brian Messenger, Karen A. Nummy, Ravi M. Todi
  • Patent number: 8692307
    Abstract: Deep trench capacitor structures and methods of manufacture are disclosed. The method includes forming a deep trench structure in a wafer comprising a substrate, buried oxide layer (BOX) and silicon (SOI) film. The structure includes a wafer comprising a substrate, buried insulator layer and a layer of silicon on insulator layer (SOI) having a single crystalline structure throughout the layer. The structure further includes a first plate in the substrate and an insulator layer in direct contact with the first plate. A doped polysilicon is in direct contact with the insulator layer and also in direct contact with the single crystalline structure of the SOI.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: April 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Joseph Ervin, Brian Messenger, Karen A. Nummy, Ravi M. Todi
  • Publication number: 20140084418
    Abstract: Deep trench capacitor structures and methods of manufacture are disclosed. The method includes forming a deep trench structure in a wafer including a substrate, buried oxide layer (BOX) and silicon (SOI) film. The structure includes a wafer including a substrate, buried insulator layer and a layer of silicon on insulator layer (SOI) having a single crystalline structure throughout the layer. The structure further includes a first plate in the substrate and an insulator layer in direct contact with the first plate. A doped polysilicon is in direct contact with the insulator layer and also in direct contact with the single crystalline structure of the SOI.
    Type: Application
    Filed: November 26, 2013
    Publication date: March 27, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joseph ERVIN, Brian MESSENGER, Karen A. NUMMY, Ravi M. TODI
  • Publication number: 20120261797
    Abstract: Deep trench capacitor structures and methods of manufacture are disclosed. The method includes forming a deep trench structure in a wafer comprising a substrate, buried oxide layer (BOX) and silicon (SOI) film. The structure includes a wafer comprising a substrate, buried insulator layer and a layer of silicon on insulator layer (SOI) having a single crystalline structure throughout the layer. The structure further includes a first plate in the substrate and an insulator layer in direct contact with the first plate. A doped polysilicon is in direct contact with the insulator layer and also in direct contact with the single crystalline structure of the SOI.
    Type: Application
    Filed: June 22, 2012
    Publication date: October 18, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joseph ERVIN, Brian MESSENGER, Karen A. NUMMY, Ravi M. TODI
  • Patent number: 8232163
    Abstract: Deep trench capacitor structures and methods of manufacture are disclosed. The method includes forming a deep trench structure in a wafer comprising a substrate, buried oxide layer (BOX) and silicon (SOI) film. The method further includes forming a plate on a sidewall of the deep trench structure in the substrate by an implant process. The implant processes contaminate exposed edges of the SOI film in the deep trench structure. The method further includes removing the contaminated exposed edges of the SOI film by an etching process to form a void in the SOI film. The method further includes growing epitaxial Si in the void, prior to completing a capacitor structure.
    Type: Grant
    Filed: November 1, 2010
    Date of Patent: July 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Joseph Ervin, Brian Messenger, Karen A. Nummy, Ravi M. Todi
  • Publication number: 20120104547
    Abstract: Deep trench capacitor structures and methods of manufacture are disclosed. The method includes forming a deep trench structure in a wafer comprising a substrate, buried oxide layer (BOX) and silicon (SOI) film. The method further includes forming a plate on a sidewall of the deep trench structure in the substrate by an implant process. The implant processes contaminate exposed edges of the SOI film in the deep trench structure. The method further includes removing the contaminated exposed edges of the SOI film by an etching process to form a void in the SOI film. The method further includes growing epitaxial Si in the void, prior to completing a capacitor structure.
    Type: Application
    Filed: November 1, 2010
    Publication date: May 3, 2012
    Applicant: International Business Machines Corporation
    Inventors: JOSEPH ERVIN, Brian Messenger, Karen A. Nummy, Ravi M. Todi
  • Patent number: 7446005
    Abstract: A manufacturable way to recess silicon that employs an end point detection method for the recess etch and allows tight tolerances on the recess is described for fabricating a strained raised source/drain layer. The method includes forming a monolayer oxygen and carbon on a surface of a doped semiconductor substrate; forming an epi Si layer atop the doped semiconductor substrate; forming at least one gate region on the epi Si layer; selectively etching exposed portions of the epi layer, not protected by the gate region, stopping on and exposing the doped semiconductor substrate using end point detection; and forming a strained SiGe layer on the exposed doped semiconductor substrate. The strained SiGe layer severs as a raised layer in which source/drain diffusion regions can be subsequently formed.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: November 4, 2008
    Assignee: International Business Machines Corporation
    Inventors: Brian Messenger, Renee T. Mo, Dominic J. Schepis
  • Publication number: 20070246442
    Abstract: A method for removing damages of a dual damascene structure after plasma etching is disclosed. The method comprises the use of sublimation processes to deposit reactive material onto the damaged regions and conditions to achieve a controlled removal of the damaged region. Furthermore a semiconductor structure comprising a dual damascene structure that has been treated by the method is disclosed.
    Type: Application
    Filed: April 20, 2006
    Publication date: October 25, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: William America, Steven Johnston, Brian Messenger
  • Publication number: 20070115974
    Abstract: An optical network packet classification architecture is disclosed that addresses the packet classification requirements for OC-768 optical routers and beyond. The herein disclosed system is used for ultra-high speed packet classification of optical data at either the serial data stream level for maximum performance, or after it has been converted into parallel words of data. The presently preferred embodiment of the invention provides a system that operates in the receive path, where electronic data are provided by the optical interface to the data framer. The invention incorporates unique features into a traditional optical data framer chip and relies on a complex ASIC to permit the user to differentiate between up to 10,000 different patterns at ultra-high speeds. One purpose of the general purpose system disclosed herein is to eliminate the need for costly and power consumptive content addressable memory systems, or customer pattern specific ASICs, to perform network packet classification.
    Type: Application
    Filed: December 14, 2006
    Publication date: May 24, 2007
    Inventor: Brian Messenger
  • Publication number: 20070078288
    Abstract: A process for the production of an olefin comprising partially combusting in a reaction zone a mixture of a hydrocarbon and an oxygen-containing gas in the presence of a catalyst which is capable of supporting combustion beyond the fuel rich limit of flammability to produce the olefin, wherein the superficial feed velocity of said mixture is at least 250 cm s?-l? at standard temperature and operating pressure with the proviso that where the catalyst is an unsupported catalyst, the superficial feed velocity of said mixture is at least 300 cm s?1 at standard temperature and operating pressure.
    Type: Application
    Filed: November 21, 2006
    Publication date: April 5, 2007
    Applicant: Ineos Europe Limited
    Inventors: David Griffiths, Ian Little, Brian Messenger, Ian Reid
  • Publication number: 20070077702
    Abstract: A process is provided for forming a trench capacitor, such as used in a DRAM memory cell, in which the required number of polysilicon deposition steps and planarization steps are reduced. A first region of a first material is formed in the bottom portion of the trench, and a dielectric material for the collar structure is subsequently formed above this region on a portion of the trench sidewalls. A removable material, such as a resist or spin-on glass, is then provided in the trench, overlying the first material and in contact with the lower portion of the collar dielectric material. The upper portion of the collar structure is then removed, after which the removable material is removed to again expose the upper surface of the first region. A second region of a second material, overlying and in contact with the first region, is then formed; the second region has an upper surface below the surface of the substrate. The first and second materials are conducting materials, typically polysilicon.
    Type: Application
    Filed: October 10, 2006
    Publication date: April 5, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Brian Messenger
  • Patent number: 7153738
    Abstract: A process is provided for forming a trench capacitor, such as used in a DRAM memory cell, in which the required number of polysilicon deposition steps and planarization steps are reduced. A first region of a first material is formed in the bottom portion of the trench, and a dielectric material for the collar structure is subsequently formed above this region on a portion of the trench sidewalls. A removable material, such as a resist or spin-on glass, is then provided in the trench, overlying the first material and in contact with the lower portion of the collar dielectric material. The upper portion of the collar structure is then removed, after which the removable material is removed to again expose the upper surface of the first region. A second region of a second material, overlying and in contact with the first region, is then formed; the second region has an upper surface below the surface of the substrate. The first and second materials are conducting materials, typically polysilicon.
    Type: Grant
    Filed: May 19, 2005
    Date of Patent: December 26, 2006
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Brian Messenger
  • Publication number: 20060263975
    Abstract: A process is provided for forming a trench capacitor, such as used in a DRAM memory cell, in which the required number of polysilicon deposition steps and planarization steps are reduced. A first region of a first material is formed in the bottom portion of the trench, and a dielectric material for the collar structure is subsequently formed above this region on a portion of the trench sidewalls. A removable material, such as a resist or spin-on glass, is then provided in the trench, overlying the first material and in contact with the lower portion of the collar dielectric material. The upper portion of the collar structure is then removed, after which the removable material is removed to again expose the upper surface of the first region. A second region of a second material, overlying and in contact with the first region, is then formed; the second region has an upper surface below the surface of the substrate. The first and second materials are conducting materials, typically polysilicon.
    Type: Application
    Filed: May 19, 2005
    Publication date: November 23, 2006
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Brian Messenger
  • Patent number: 7115955
    Abstract: A manufacturable way to recess silicon that employs an end point detection method for the recess etch and allows tight tolerances on the recess is described for fabricating a strained raised source/drain layer. The method includes forming a monolayer comprising oxygen and carbon on a surface of a doped semiconductor substrate; forming an epi Si layer atop the doped semiconductor substrate; forming at least one gate region on the epi Si layer; selectively etching exposed portions of the epi layer, not protected by the gate region, stopping on and exposing the doped semiconductor substrate using end point detection; and forming a strained SiGe layer on the exposed doped semiconductor substrate. The strained SiGe layer serves as a raised layer in which source/drain diffusion regions can be subsequently formed.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: October 3, 2006
    Assignee: International Business Machines Corporation
    Inventors: Brian Messenger, Renee T. Mo, Dominic J. Schepis
  • Publication number: 20060205189
    Abstract: A manufacturable way to recess silicon that employs an end point detection method for the recess etch and allows tight tolerances on the recess is described for fabricating a strained raised source/drain layer. The method includes forming a monolayer oxygen and carbon on a surface of a doped semiconductor substrate; forming an epi Si layer atop the doped semiconductor substrate; forming at least one gate region on the epi Si layer; selectively etching exposed portions of the epi layer, not protected by the gate region, stopping on and exposing the doped semiconductor substrate using end point detection; and forming a strained SiGe layer on the exposed doped semiconductor substrate.
    Type: Application
    Filed: May 12, 2006
    Publication date: September 14, 2006
    Applicant: International Business Machines Corporation
    Inventors: Brian Messenger, Renee Mo, Dominic Schepis
  • Publication number: 20060205989
    Abstract: The present invention provides a process for the production of olefins which process comprises co-feeding at least one unsaturated hydrocarbon with a paraffinic hydrocarbon-containing feedstock and a molecular oxygen-containing gas to an autothermal cracker, wherein they are reacted in the presence of a catalyst capable of supporting combustion beyond the normal fuel rich limit of flammability to provide a hydrocarbon product stream comprising olefins.
    Type: Application
    Filed: March 24, 2004
    Publication date: September 14, 2006
    Inventors: Ian Raymond Little, Barry Maunders, Brian Messenger
  • Publication number: 20060074268
    Abstract: A process for the production of an olefin from a hydrocarbon, which process comprises: partially combusting the hydrocarbon and an oxygen-containing gas in the presence of a catalyst, characterised in that the catalyst comprises palladium and at least one further metal, said further metal being a Group IIIA, Group IVA, VA or a transition metal.
    Type: Application
    Filed: October 24, 2005
    Publication date: April 6, 2006
    Applicant: BP Chemicals Limited
    Inventors: John Couves, David Griffiths, Brian Messenger, Ian Beattie Reid
  • Publication number: 20060069297
    Abstract: A process for the production of an olefin from a hydrocarbon, which process comprises: partially combusting the hydrocarbon and an oxygen-containing gas in the presence of a catalyst, characterised in that the catalyst comprises platinum and at least one further metal, said further metal being a Group IIIA, Group IVA, VA or a transition metal; wherein said catalyst is: a) not a platinum catalyst consisting essentially of platinum modified with Sn, Cu or mixtures thereof, and b) not a platinum catalyst consisting essentially of platinum modified with Sb or a mixture of Sb and Sn.
    Type: Application
    Filed: October 20, 2005
    Publication date: March 30, 2006
    Applicant: BP Chemicals Limited
    Inventors: John Couves, David Griffiths, Brian Messenger, Ian Reid
  • Patent number: 6995094
    Abstract: A method for etching a silicon on insulator (SOI) substrate includes opening a hardmask layer formed on an SOI layer, and etching through the SOI layer, a buried insulator layer underneath the SOI layer, and a bulk silicon layer beneath the buried insulator layer using a single etch step.
    Type: Grant
    Filed: October 13, 2003
    Date of Patent: February 7, 2006
    Assignee: International Business Machines Corporation
    Inventors: Herbert L. Ho, Mahender Kumar, Brian Messenger, Michael D. Steigerwalt
  • Publication number: 20060022266
    Abstract: A manufacturable way to recess silicon that employs an end point detection method for the recess etch and allows tight tolerances on the recess is described for fabricating a strained raised source/drain layer. The method includes forming a monolayer comprising oxygen and carbon on a surface of a doped semiconductor substrate; forming an epi Si layer atop the doped semiconductor substrate; forming at least one gate region on the epi Si layer; selectively etching exposed portions of the epi layer, not protected by the gate region, stopping on and exposing the doped semiconductor substrate using end point detection; and forming a strained SiGe layer on the exposed doped semiconductor substrate. The strained SiGe layer serves as a raised layer in which source/drain diffusion regions can be subsequently formed.
    Type: Application
    Filed: July 30, 2004
    Publication date: February 2, 2006
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian Messenger, Renee Mo, Dominic Schepis