Abstract: A method and system for systematically accessing and monitoring operating parameter signals within an IC device. A probe configuration logic selects a subset of signals from among a set of available signals within a physical or logical subdivision of the IC device. Signal access logic selectively provides physical or logical access from the selected subset of signals within the physical or logical subdivision of the IC device to a probe sensor, such that IC device operations may be flexibly and comprehensively monitored. A local mode selector provides remote access to the selected subset of signals at an input/output (I/O) data interface. Data packaging logic in communication with the probe sensor permits port mirroring of the I/O data interface.

Abstract: A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a plurality of memory elements and a plurality of interface processors formed on a semiconductor substrate. The memory elements and interface processors together form a network processor capable of cooperating with other elements in executing instructions directing the flow of data in a network. Access to the memory elements is controlled in a particular manner and under operative rules which provide controlled multiple accesses of the plurality of memory elements by the plurality of processors.

Abstract: A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation among a plurality of interface processors and a suite of peripheral elements formed on a semiconductor substrate. The interface processors and peripherals together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network.

Abstract: A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation among a plurality of interface processors and a suite of peripheral elements formed on a semiconductor substrate. The interface processors and peripherals together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network.

Abstract: A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation among a plurality of interface processors and a suite of peripheral elements formed on a semiconductor substrate. The interface processors and peripherals together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network.

Abstract: A system and method of moving information units from an output flow control toward a data transmission network in a prioritized sequence which accommodates several different levels of service. The present invention includes a method and system for scheduling the egress of processed information units (or frames) from a network processing unit according to service based on a weighted fair queue where position in the queue is adjusted after each service based on a weight factor and the length of frame, a process which provides a method for and system of interaction between different calendar types is used to provide minimum bandwidth, best effort bandwidth, weighted fair queuing service, best effort peak bandwidth, and maximum burst size specifications. The present invention permits different combinations of service that can be used to create different QoS specifications.

Abstract: Methods, systems and computer program products are provided which control message storms in a network by classifying multiple destination messages into a plurality of broadcast message classes based upon characteristics of the broadcast messages. The number of multiple destination messages for each class of broadcast messages of the plurality of classes of broadcast messages are then counted so as to provide a plurality of broadcast message class counts. Multiple destination messages of a class of broadcast messages are then selectively transmitted based upon the broadcast message class count for the class of broadcast messages.

Abstract: A device for interconnecting Local Area Networks (LANs) includes ports for attaching LAN segments and port modules for connecting the ports to a switch fabric. Each of the port modules include a mechanism which searches the Routing Information (RI) field of a Received frame to detect at least two Triplets (a minimum configuration for a LAN segment) indicating a Source path from an originator user and a Destination path to a destination user. The Triplet (single or in combination) is used to access a database (tables) which identifies the Port of Exit (POE) through which the frame is to be routed.

Abstract: Method and system for controlling the state of a system bus during live insertion and removal of a pluggable feature card (FC) by driving control signals, which are transferred over the system bus, to an active signal level, or by driving down level active control signals to a low signal level near ground level. By this mechanism, the system bus becomes immune to signal disturbances and thereby allows pluggable units to be live inserted and removed without causing adverse effects to the system such as a system reset or compromise of data integrity. During live insertion or removal, a Live Insertion Bus Controller (LIBC) acquires access to the system bus through its interface with a System Bus Controller (SBC), after it has been signalled by a live insertion mechanism associated with the FC that the FC is in the process of being live inserted or removed.

Abstract: Method and system for controlling the state of a system bus during live insertion and removal of a pluggable feature card (FC) by driving control signals, which are transferred over the system bus, to an active signal level, or by driving down level active control signals to a low signal level near ground level. By this mechanism, the system bus becomes immune to signal disturbances and thereby allows pluggable units to be live inserted and removed without causing adverse effects to the system such as a system reset or compromise of data integrity. During live insertion or removal, a Live Insertion Bus Controller (LIBC) acquires access to the system bus through its interface with a System Bus Controller (SBC), after it has been signalled by a live insertion mechanism associated with the FC that the FC is in the process of being live inserted or removed.

Abstract: A method for improving the performance of an existing busoriented computer system with minimum or no design change to the existing hardware, bus protocol, or bus operation is disclosed. Specifically, the present invention improves the effective bandwidth of an existing bus architecture by creating multiple physical instantiations of the existing bus and directing traffic onto these different buses based on the type of bus operation being performed. This results in multiple components having the capability to simultaneously perform bus operations, therefore improving the effective bandwidth of the system. This invention also allows the components which are current being utilized in the existing bus architecture to be re-utilized with minimum additional external logic.

Abstract: A LAN switching system includes an Address Match Control line which can be set (activated) and is monitored by each port adapter card. If a port adapter card recognizes an address on the switch fabric, the adapter card copies the frame with the address and activates the Address match Control line. The set Address Match Control line causes the remaining port adapter cards to stop searching for a match. If the Address Match Control line is not set, the frame can be copied by all port adapters which are configured to do so.